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mc92610um/d 3/2003 rev. 1 mc92610 quad 3.125 gbaud serdes user?s manual device supported: MC92610VF f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-480-768-2130 (800) 521-6274 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: (800) 521-6274 home page: www.motorola.com/semiconductors motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview transmitter receiver system design considerations package description index test features electrical specifications and characteristics 1 2 3 4 5 6 7 ind glossary of terms and abbreviations glo 8b/10b coding scheme ordering information a b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview transmitter receiver system design considerations package description glossary of terms and abbreviations index 1 2 3 4 5 6 7 glo ind test features electrical specifications and characteristics 8b/10b coding scheme a b ordering information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents section number title page number motorola contents v contents paragraph number title page number about this book audience .............................................................................................................. xiii organization......................................................................................................... xiii suggested reading............................................................................................... xiv general information..................................................................................... xiv related documentation ............................................................................... xiv conventions ...........................................................................................................xv signals....................................................................................................................xv chapter 1 introduction 1.1 overview.............................................................................................................. 1-1 1.2 features ................................................................................................................ 1-1 1.3 block diagram ..................................................................................................... 1-2 1.4 references............................................................................................................ 1-4 1.5 revision history .................................................................................................. 1-4 chapter 2 transmitter 2.1 block diagram ..................................................................................................... 2-1 2.2 transmitter interface signals ............................................................................... 2-2 2.3 functional description......................................................................................... 2-5 2.3.1 transmit data input register operation.......................................................... 2-5 2.3.1.1 transmitting uncoded data......................................................................... 2-5 2.3.1.2 transmitting pre-coded data ...................................................................... 2-6 2.3.1.3 link multiplexer mode................................................................................ 2-6 2.3.1.4 repeater mode............................................................................................. 2-7 2.3.1.5 transmit interface clock configuration...................................................... 2-7 2.3.1.6 8b/10b encoder operation.......................................................................... 2-7 2.3.1.7 transmit driver operation........................................................................... 2-8 2.3.1.8 transmit equalization.................................................................................. 2-8 2.3.1.9 loop-back test mode ................................................................................. 2-9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number vi mc92610 serdes user?s manual motorola chapter 3 receiver 3.1 receiver block diagram...................................................................................... 3-1 3.2 receiver interface signals ................................................................................... 3-2 3.3 receiver functional description ......................................................................... 3-5 3.3.1 input amplifier ................................................................................................ 3-6 3.3.1.1 receiver equalization .................................................................................. 3-7 3.3.1.2 loop-back test mode ................................................................................. 3-7 3.3.2 transition tracking loop and data recovery................................................. 3-8 3.3.3 byte alignment................................................................................................ 3-8 3.3.3.1 byte alignment and realignment method .................................................. 3-8 3.3.3.2 non-aligned method................................................................................... 3-9 3.3.4 word synchronization ..................................................................................... 3-9 3.3.4.1 word synchronization method.................................................................. 3-10 3.3.4.2 word synchronization bus ........................................................................ 3-11 3.3.4.3 multi-chip word synchronization ............................................................ 3-11 3.3.4.4 recommended mode states for word synchronization............................ 3-12 3.3.5 8b/10b decoder ............................................................................................ 3-13 3.3.6 receiver interface .......................................................................................... 3-13 3.3.6.1 byte interface............................................................................................. 3-14 3.3.6.2 ten-bit interface ........................................................................................ 3-14 3.3.6.3 receiver interface error codes ................................................................. 3-14 3.3.7 receiver interface clock timing modes....................................................... 3-15 3.3.7.1 recovered clock timing mode................................................................. 3-16 3.3.7.2 reference clock timing mode.................................................................. 3-16 3.3.8 half-speed mode........................................................................................... 3-17 3.3.9 repeater mode............................................................................................... 3-17 3.3.10 link multiplexer mode.................................................................................. 3-17 chapter 4 system design considerations 4.1 reference clock configuration ........................................................................... 4-1 4.2 startup .................................................................................................................. 4-2 4.3 repeater mode ..................................................................................................... 4-2 4.3.1 ten-bit interface mode.................................................................................... 4-2 4.3.2 byte alignment mode ..................................................................................... 4-3 4.3.3 word synchronization mode ........................................................................... 4-3 4.3.4 recovered clock timing mode....................................................................... 4-3 4.3.5 reference clock timing mode........................................................................ 4-4 4.3.6 half-speed mode, double data rate mode.................................................... 4-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number motorola contents vii 4.4 configuration and control signals ...................................................................... 4-4 4.5 power supply requirements................................................................................ 4-5 4.6 phase locked loop (pll) power supply filtering............................................. 4-5 4.7 power supply decoupling recommendations .................................................... 4-6 4.8 hstl reference voltage recommendation ........................................................ 4-6 4.8.1 voltage reference for single-ended reference clock use............................. 4-7 4.9 impedance control reference recommendation ................................................ 4-7 chapter 5 test features 5.1 ieee std. 1149.1 implementation ....................................................................... 5-1 5.1.1 test access port (tap) interface signals ........................................................ 5-1 5.1.2 instruction register.......................................................................................... 5-2 5.1.3 instructions....................................................................................................... 5-2 5.1.4 boundary-scan register .................................................................................. 5-3 5.1.5 device identification register (0x0280e01d) ................................................ 5-3 5.1.6 performance ..................................................................................................... 5-3 5.2 system accessible test modes ............................................................................ 5-3 5.2.1 loop back system test ................................................................................... 5-4 5.2.2 bist sequence system test mode.................................................................. 5-4 5.3 loop-back bist sequence system test mode................................................... 5-6 chapter 6 electrical specifications and characteristics 6.1 general characteristics ........................................................................................ 6-1 6.1.1 general parameters .......................................................................................... 6-1 6.1.2 absolute maximum ratings ............................................................................ 6-1 6.1.3 recommended operating conditions.............................................................. 6-2 6.2 dc electrical specifications ................................................................................ 6-3 6.3 ac electrical characteristics............................................................................... 6-4 6.3.1 parallel port interface timing.......................................................................... 6-4 6.3.2 word synchronization bus timing.................................................................. 6-6 6.3.3 reference clock timing .................................................................................. 6-7 6.3.4 receiver recovered clock timing .................................................................. 6-8 6.3.5 serial data link timing .................................................................................. 6-9 6.3.6 jtag test port timing .................................................................................. 6-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents viii mc92610 serdes user?s manual motorola chapter 7 package description 7.1 324 mapbga package parameter summary ..................................................... 7-1 7.2 nomenclature and dimensions of the 324 mapbga package .......................... 7-1 7.3 package thermal characteristics......................................................................... 7-5 7.4 mc92610 chip pinout listing............................................................................. 7-5 appendix a ordering information appendix b 8b/10b coding scheme b.1 overview..............................................................................................................b-1 b.1.1 naming transmission characters ....................................................................b-2 b.1.2 encoding ..........................................................................................................b-2 b.1.3 calculating running disparity ........................................................................b-3 b.2 data tables...........................................................................................................b-3 glossary of terms and abbreviations index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
figures figure number title page number motorola figures ix 1-1 mc92610 block diagram ........................................................................................... 1-3 2-1 mc92610 transmitter block diagram ....................................................................... 2-2 3-1 mc92610 receiver block diagram............................................................................ 3-2 4-1 pll power supply filter circuits............................................................................... 4-6 4-2 hstl class-i vref circuit ....................................................................................... 4-7 4-3 impedance reference circuit...................................................................................... 4-8 5-1 instruction register ..................................................................................................... 5-2 5-2 device identification register .................................................................................... 5-3 6-1 transmitter ddr interface timing............................................................................. 6-4 6-2 transmitter interface sdr timing diagram (lme = high, ddre = low).............. 6-5 6-3 receiver interface ddr timing diagram .................................................................. 6-5 6-4 receiver interface sdr timing diagram (lme = high, ddre = low) .................. 6-6 6-5 word synchronization bus timing diagram.............................................................. 6-7 6-6 reference clock timing diagram .............................................................................. 6-7 6-7 recovered clock timing diagram ............................................................................. 6-8 6-8 link differential output timing diagram.................................................................. 6-9 6-9 link differential input timing diagram .................................................................... 6-9 6-10 jtag i/o timing diagram ....................................................................................... 6-10 7-1 324 mapbga nomenclature ..................................................................................... 7-2 7-2 mapbga dimensions ............................................................................................... 7-3 7-3 324 mapbga package .............................................................................................. 7-4 a-1 motorola part number key........................................................................................ a-1 b-1 unencoded transmission character bit ordering ......................................................b-1 b-2 encoded transmission character bit ordering ..........................................................b-2 b-3 character transmission...............................................................................................b-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
figures figure number title page number x mc92610 serdes user?s manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
tables table number title page number motorola tables xi 1-1 mc92610 serdes user?s manual revision history................................................ 1-4 2-1 mc92610 transmitter interface signals ..................................................................... 2-3 2-2 transmitter control states .......................................................................................... 2-6 3-1 receiver interface signals ......................................................................................... 3-3 3-2 word synchronization states .................................................................................... 3-12 3-3 receiver interface error codes (byte interface) ...................................................... 3-15 3-4 receiver interface error codes (ten-bit interface).................................................. 3-15 4-1 legal reference clock frequency ranges ................................................................. 4-1 4-2 startup sequence step duration.................................................................................. 4-2 4-3 asynchronous configuration and control signals ..................................................... 4-4 5-1 tap interface signals ................................................................................................. 5-1 5-2 tap controller public instructions .............................................................................. 5-2 5-3 tap controller private instruction codes.................................................................... 5-3 5-4 test mode state selection ........................................................................................... 5-3 5-5 bist error codes........................................................................................................ 5-5 6-1 absolute maximum ratings ....................................................................................... 6-1 6-2 recommended operating conditions ......................................................................... 6-2 6-3 dc electrical specifications ....................................................................................... 6-3 6-4 transmitter ddr timing specification ...................................................................... 6-4 6-5 transmitter sdr timing specification (lme = high, ddre = low)...................... 6-5 6-6 receiver ddr timing specification .......................................................................... 6-5 6-7 receiver sdr timing specification (lme = high, ddre = low) .......................... 6-6 6-8 word synchronization bus timing specification....................................................... 6-7 6-9 reference clock specification.................................................................................... 6-8 6-10 recovered clock specification ................................................................................... 6-8 6-11 link differential output specification ....................................................................... 6-9 6-12 link differential input timing specification ........................................................... 6-10 6-13 jtag i/o timing specification ................................................................................ 6-11 7-1 package thermal resistance values ........................................................................... 7-5 7-2 324 mapbga signal to ball mapping ...................................................................... 7-5 b-1 components of a character name ..............................................................................b-2 b-2 valid data characters..................................................................................................b-4 b-3 valid special characters .............................................................................................b-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
tables table number title page number xii mc92610 serdes user?s manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola about this book xiii about this book the primary objective of this user?s manual is to describe the functionality of the mc92610 for software and hardware developers. information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. as with any technical documentation, it is the readers? responsibility to be sure they are using the most recent version of the documentation. audience it is assumed that the reader has the appropriate general knowledge regarding the design and layout requirements for high speed (gbps) digital signaling and understanding of the basic principles of ethernet and fibre channel communications protocols to use the information in this manual. organization following is a summary and a brief description of the major sections of this manual: chapter 1, ?introduction,? is useful for software and hardware engineers who need to have a general understanding of how the part works. chapter 2, ?transmitter,? describes the mc92610 transmitter, its interfaces and operation. chapter 3, ?receiver,? gives a description of the receiver. chapter 4, ?system design considerations,? describes the system considerations for the mc92610, including clock configuration, device startup and initialization, and proper use repeater mode. chapter 5, ?test features,? covers the jtag implementation and the system accessible test modes. chapter 6, ?electrical specifications and characteristics,? describe the dc and ac electrical characteristics. chapter 7, ?package description,? provides the package parameters and mechanical dimensions of the mc92610 device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xiv mc92610 serdes user?s manual motorola appendix a, ?ordering information,? provides the motorola part numbering nomenclature for the mc92610 transceiver appendix b, ?8b/10b coding scheme,? provides fibre channel-specific 8b/10b encoding and decoding based on the ansi fc-1 fibre channel standard. ?glossary of terms and abbreviations? contains an alphabetical list of terms, phrases, and abbreviations used in this book. suggested reading this section lists additional reading that provides background for the information in this manual as well as general information about the architecture. general information the following documentation, published by morgan-kaufmann publishers, 340 pine street, sixth floor, san francisco, ca, provides useful information about the powerpc architecture and computer architecture in general: the powerpc architecture: a specification for a new family of risc processors , second edition, by international business machines, inc. for updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html. computer architecture: a quantitative approach , second edition, by john l. hennessy and david a. patterson computer organization and design: the hardware/software interface , second edition, david a. patterson and john l. hennessy related documentation motorola documentation is available from the sources listed on the back cover of this manual; the document order numbers are included in parentheses for ease in ordering: user?s manuals and reference manuals?these books provide details about individual device implementations. the mc92610dvb serdes design verification board reference manual (mc92610dvbrm/d) describes how to use the design verification board and should be read in conjunction with this manual, the mc92610 quad 3.125 gbaud serdes user?s manual (mc92610um/d). addenda/errata to user?s manuals?because some devices have follow-on parts an addendum is provided that describes the additional features and functionality changes. these addenda are intended for use with the corresponding user?s manuals. hardware specifications?hardware specifications provide specific data regarding bus timing, signal behavior, and ac, dc, and thermal characteristics, as well as other design considerations. this manual contains all of the hardware specifications for the mc92610. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola about this book xv application notes?these short documents address specific design issues useful to programmers and engineers working with motorola processors. white paper-these documents provide detail on a specific design platform and are useful to programmers and engineers working on a specific product. mc92610 3.125 gbaud reference design platform (br1570/d) describes the technical design process used in developing a high speed backplane. additional literature is published as new processors become available. for a current list of documentation, refer to http://www.motorola.com/semiconductors. conventions this document uses the following notational conventions: book titles in text are set in italics internal signals are set in italics, for example, qual bg 0x prefix to denote hexadecimal number 0b prefix to denote binary number x in some contexts, such as signal encodings, an un-italicized x indicates a don?t care. x an italicized x indicates an alphanumeric variable. n an italicized n indicates an numeric variable. signals a bar over a signal name indicate that the signal is active low?for example, xmit_a_idle and xmit_b_idle . active low signals are referred to as asserted (active) when they are low and negated when they are high. signals that are not active low, such as xmit_eq_en and drop_sync are referred to as asserted when they are high and negated when they are low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xvi mc92610 serdes user?s manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 1. introduction 1-1 chapter 1 introduction this user?s manual explains the functionality of the mc92610 quad 3.125 gbaud serdes transceiver and enable its use by software and hardware developers. the audience for this publication, therefore, consists of developers and application programmers who are building data path switches and applications. 1.1 overview the mc92610, is a high-speed, full-duplex, serial/deserializer (serdes) data interface device that transmits data between chips across a board, through a backplane, or through cabling. the mc92610 has four transceivers that transmit and receive coded data at a maximum rate of 2.5 gigabits per second (gbps) through each 3.125 gigabaud link. each transceiver has redundant transmit and receive i/os that are independently selectable. the mc92610 features hstl class 1 ddr source synchronous parallel interfaces that allow efficient integration with system logic. the mc92610 is designed to minimize the number of data line interconnects in point-to-point communications with low power requirements. the mc92610 serdes offers high performance with excellent signal integrity and low bit-error-rate (ber). other features include clock generation and recovery, on-chip termination resistors and coupling capacitors, low transmit jitter, and multiple modes of operation - within a compact 324-pin mapbga package. the mc92610 features make it advantageous for use in many different data transfer designs. this in turn simplifies the architectures of switch backplanes while enabling small footprint designs. the mc92610 serdes is the latest generation of motorola?s products. like its predecessors, it features a very low power 0.25 cmos implementation, using 1.8 watts. with all links operating at full-speed. with a high-density packaging solution and a rich feature set the mc92610 is easily adaptable to many applications. 1.2 features the following are the features of the mc92610: 4 full-duplex differential data links. selectable speed range: 3.125 gbaud or 1.5625 gbaud. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-2 mc92610 serdes user?s manual motorola block diagram low power, nominally 1.8w, while operating all transceivers at full speed. internal 8b/10b encoder / decoder that can be bypassed for applications where external coding is used. double data rate (ddr), source synchronous, 8-bit and 10-bit hstl class-1 parallel data interfaces. received data may be clocked at the recovered clock or the reference clock frequency. link-to-link synchronization supports aligned, 32-bit, word transfers. the synchronization mechanism can tolerates up to 40 bit-times of link-to-link media delay skew. multi-chip link synchronization supports aligned, multi-word transfers. up to four mc92610 devices may be used to provide 128-bit, four-word, synchronized transfers. selectable idle character alignment mode enables aligned transfers with automatic realignment or unaligned data transfers. transceiver links operate over 50 ? media (100 ? differential) for lengths of up to one meter of fr-4 board/backplane or six meters of coax. selectable transmit and receive link equalization. link inputs have on-chip receiver termination, ac coupling and are ?hot swap? compatible. redundant transmitter outputs and receiver inputs are provided. redundant links are selectable per transceiver. broadcast mode enables all transmit link outputs. differential reference clock input with single-ended reference clock input option. link multiplexer mode enables operation of two links with single data rate (sdr), source synchronous, 16-bit and 20-bit parallel data interfaces. transceiver channels may be individually disabled. repeater mode configures the mc92610 into a four-link receive-transmit repeater. at speed built-in self test (bist) for in-system diagnostics. ieee 1149.1 jtag boundary scan test support. 1.3 block diagram the mc92610 is a highly integrated device containing all of the logic needed to facilitate the application and test of a high-speed serial interface. a block diagram of the mc92610 device is shown in figure 1-1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 1. introduction 1-3 block diagram figure 1-1. mc92610 block diagram xlink_a0_n xlink_a0_p rlink_a1_p rlink_a1_n xmit_a[7:0], xmit_a_k, xmit_a_idle xmit_a_clk 8b/10b xlink_a1_n xlink_a1_p rlink_a0_p rlink_a0_n transmit recv_a[7:0], recv_a_k, recv_a_9, recv_a_idle, recv_a_err recv_a_clk xcvr_a_disable, xcvr_a_rsel recv_eq_en, xmit_eq_en interface unit encoder receive interface unit transmitter receiver config: tbie, hse, ddre, lme, repe, bsync, rcce, adie, wse, xmit_en_all, xmit_ref_a, recv_ref_a 8b/10b decoder xlink_b0_n xlink_b0_p rlink_b1_p rlink_b1_n xmit_b_clk 8b/10b xlink_b1_n xlink_b1_p rlink_b0_p ref_clk_p transmit recv_b[7:0], recv_b_k, recv_b_9, recv_b_idle, recv_b_err recv_b_clk xcvr_b_disable, xcvr_b_rsel interface unit encoder receive interface unit transmitter receiver 8b/10b decoder test: tst_0, tst_1, bist_mode_sel, lbe, lboe, scan_en, tx_pll_tpa drop_sync, reset wsi wso tdo, tdi, tms, trst , tck xlink_c0_n xlink_c0_p rlink_c1_p rlink_c1_n xmit_c[7:0], xmit_c_k, xmit_c_idle xmit_c_clk 8b/10b xlink_c1_n xlink_c1_p rlink_c0_p rlink_c0_n recv_c[7:0], recv_c_k, recv_c_9, recv_c_idle, recv_c_err recv_c_clk xcvr_c_disable, xcvr_c_rsel encoder receive interface unit transmitter receiver 8b/10b decoder xlink_d0_n xlink_d0_p rlink_d1_p rlink_d1_n xmit_d_clk 8b/10b xlink_d1_n xlink_d1_p rlink_d0_p rlink_d0_n transmit recv_d[7:0], recv_d_k, recv_d_9, recv_d_idle, recv_d_err recv_d_clk xcvr_d_disable, xcvr_d_rsel interface unit encoder receive interface unit transmitter receiver 8b/10b decoder system integration unit jtag xmit_b[7:0], xmit_b_k, xmit_b_idle xmit_d[7:0], xmit_d_k, xmit_d_idle system pll ref_clk_n rlink_b0_n transmit interface unit , tck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-4 mc92610 serdes user?s manual motorola references 1.4 references this section contains the indexed references in the document. [1] fibre channel, gigabit communications and i/o for computer networks , brenner, 1996. [2] byte oriented dc balanced 8b/10b partitioned block transmission code , u.s. patent #4,486,739, dec. 4, 1984. [3] high speed transceiver logic (hstl), a 1.5v output buffer supply voltage based interface standard for digital integrated circuits, eia/jedic standard eia/jesd8-6, aug. 1995. [4] ieee standard test access port and boundary-scan architecture, ieee std. 1149.1-1990 (includes ieee std. 1149.1a-1993), oct. 1993. 1.5 revision history table 1-1 contains a brief description of the technical updates made to this document. table 1-1. mc92610 serdes user?s manual revision history revision level change 0 first revision of the mc92610 serdes user?s manual. 1 second revision of the mc92610 serdes user?s manual. minor edits were made to the entire document. added note in section 5.1, ?ieee std. 1149.1 implementation,? and section 5.2.2, ?bist sequence system test mode.? changed supply currents, power dissipation, min/max latencies in chapter 6, ?electrical specifications and characteristics.? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 2. transmitter 2-1 chapter 2 transmitter this chapter describes the mc92610 transmitter, its interfaces and operation. the chapter consists of the following sections: section 2.1, ?block diagram? section 2.2, ?transmitter interface signals? section 2.3, ?functional description.? the transmitter takes the data byte presented at its data input, creates a transmission character using its 8b/10b encoder (if not in 10-bit interface mode), and serially transmits the character out of the differential link output pads. a detailed explanation of the 8b/10b coding scheme is offered in appendix b, ?8b/10b coding scheme.? 2.1 block diagram figure 2-1 shows a block diagram of the mc92610 transmitter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-2 mc92610 serdes user?s manual motorola transmitter interface signals . 2.2 transmitter interface signals this section describes the interface signals of the mc92610 transmitters. each signal is described, including its name, function, direction, and active state in table 2-1. the table?s signal names use the letter ? x ? as a place holder for the link identifier letter ?a? through ?d?. internal signals are not available at the i/o of the device, but are presented to illustrate device operation. figure 2-1. mc92610 transmitter block diagram xmit driver xcvr_ x _disable xmit driver loop_back_data xmit_en_all xcvr_ x _rsel xmit_eq_en hse repe lme ddre transmitter controller xlink_ x 0_p xlink_ x 0_n xlink_ x 1_p xlink_ x 1_n 8b/10b encoder serialization register tbie lboe lbe tst_1 tst_0 rx_clock input register input register xmit_ref_a xmit_a_clk xmit_ x _clk bist sequence generator link_mux_data repeat_data xmit_ x _[7:0] xmit_ x _k xmit _ x _idle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 2. transmitter 2-3 transmitter interface signals table 2-1. mc92610 transmitter interface signals signal name description function direction active state xmit_ x _7 through xmit_ x _0 transmit byte uncoded data/control byte to transmit. the least significant 8 bits of the pre-coded data transmits in tbi (ten bit interface) mode. input - xmit_ x _k special data indicator indicates that transmit byte is a special control byte. must be decoded with xmit _ x _idle to determine action, see tab l e 2 - 2. pre-coded transmit data bit 8 in tbi mode. input high xmit _ x _idle transmit idle character bar transmit an idle character. must be decoded with xmit_ x _k to determine action, see table 2-2. pre-coded transmit data bit 9 in tbi mode. input low xmit_ x _clk transmit interface clock clock to which transmit interface signals are timed. frequency requirement is dependent on whether hse and ddre are asserted. see section 4.1 and table 4-1 for configuration options. input - xmit_ref_a transmit interface clock select indicates that the transmit interface signals are timed to xmit_a_clk instead of their transmit clock. input high xcvr_ x _disable transceiver disable indicates that the transmitter and receiver for this transceiver are disabled. the link outputs are not driven. input high xcvr_ x _rsel transceiver link select indicates that the redundant link outputs are active and that the primary link outputs are disabled. the primary link outputs are active and the redundant link outputs are disabled when this signal is low. both sets of outputs may be simultaneously enabled using the xmit_en_all signal. input high xmit_en_all transmitter link broadcast enable indicates that both the primary and redundant link outputs are enabled independent of the assertion of the xcvr_ x _rsel signal. broadcast mode does not override xcvr_ x _disable, which must be set low for transmitter operation. input high xmit_eq_en transmit equalization enable indicates that transmitter equalization is enabled and that high frequency gain is applied to the transmitted signal. input high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-4 mc92610 serdes user?s manual motorola transmitter interface signals tbie ten-bit interface enable indicates that pre-coded 10-bit data is at inputs and to bypass internal 8b/10b coding. input high repe repeater mode enable when enabled, the transmitter obtains transmit data from the receiver. input high lme link multiplexer mode enable indicates that the data on transmitter a and b are aggregated and transmit out of link a. likewise, the data on transmitter c and d are aggregated and transmit out of link c. input high ddre double data rate enable when in link multiplexer mode (lme signal is high) this signal indicates that the data interfaces are running at double data rate. when not in link multiplexer mode, this signal does not affect device operation. input high hse half speed enable when enabled, link is operated at half-speed. both data and link interfaces run at half speed. input high lbe loop back enable activate digital loopback path, such that data transmitted is looped back to its receiver. input high lboe loop back output enable indicates that selected link outputs remain active when loop back is enabled. the link outputs are disabled when lboe is low and loop back is enabled. input high tst_1, tst_0 test mode select selects a test mode. input - xlink_ x 0_n/ xlink_ x 0_p link serial transmit data, primary links differential serial transmit data output pads for the primary links. output - xlink_ x 1_n/ xlink_ x 1_p link serial transmit data, redundant links differential serial transmit data output pads for the redundant links. output - internal signals rx_clock high speed transceiver clock internal, differential high speed clock used to transmit and receive link data. input - repeat_data received repeat data repeater mode, received data to retransmit. input - link_mux_data link multiplexer mode data data from adjacent transmitter to transmit on this transmitter when in link multiplexer mode (lme is asserted.) input - loop_back_data loop back data differential loop back transmit data. output - table 2-1. mc92610 transmitter interface signals (continued) signal name description function direction active state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 2. transmitter 2-5 functional description 2.3 functional description the transmitter takes the data byte presented at its data input, creates a transmission character using its 8b/10b encoder and serially transmits the character out of the differential link output pads. the following sections provide a detailed description of the transmitter and its modes of operation. 2.3.1 transmit data input register operation the transmit data input register accepts data to be transmitted and synchronizes it to the internal clock domain. transmit data is normally uncoded 8-bit data, however, transmission of pre-coded 10-bit data is supported in ten-bit interface (tbi) mode. tbi mode is enabled by asserting tbie high. the transmit data interface is a double data rate (ddr) interface; the data is sampled and stored on the rising and falling edges of the transmit interface clock xmit_ x _clk. there are several clocking options on the transmit data interface that are described in section 2.3.1.5. 2.3.1.1 transmitting uncoded data uncoded data is presented in 8-bit bytes to the input register through the xmit_ x _7? xmit_ x _0 signals. the uncoded data is coded into 10-bit transmission characters using an on-chip 8b/10b encoder. 8b/10b coding ensures dc balance across the link and sufficient transition density to facilitate reliable data recovery. the xmit_ x _7?xmit_ x _0 signals are interpreted as data when the xmit_ x _k signal is low. the 8b/10b code includes special control codes. special control codes may be transmitted by asserting xmit_ x _k high, and xmit_ x _idle high as indicated in table 2-2. the transmit byte is assumed to be a control code in this state. the transmitter generates an idle character (k28.5) when xmit_ x _k is high and xmit_ x _idle is low as indicated in table 2-2. an idle character of proper running disparity is generated when this state is asserted; the state on the xmit_ x _7?xmit_ x _0 signals are ignored. this eases generation of idle characters needed for byte and word synchronization and allows the link to maintain alignment when transmission of data is not needed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-6 mc92610 serdes user?s manual motorola functional description 2.3.1.2 transmitting pre-coded data ten-bit pre-coded data may be transmitted, bypassing the internal 8b/10b encoder. ten-bit interface (tbi) mode is enabled by asserting tbie high. in this mode, the ten bits to transmit are presented on the xmit_ x _7?xmit_ x _0 inputs, and bits 8 and 9 on the xmit_ x _k and xmit_ x _idle inputs, respectively. precautions must be taken when using tbi mode. the 10-bit pre-coded data must exhibit the same properties as 8b/10b coded data. dc balance must be maintained and there must be sufficient transition density to ensure reliable data recovery at the receiver. the receiver requires that the k28.5 idle character be periodically transmitted to enable byte and word synchronization. this 10-bit pattern, ?0011111010? or ?1100000101? (ordered from bit 0 through 9) is used for alignment and link-to-link synchronization when operating in any of the byte or word synchronization modes. the pattern of idles and data required to achieve byte or word synchronization depends on the configuration of the receiver, see section 3.3.4.3. the appropriate sequence must be applied through the ten-bit interface. the mc92610 transmitter is comprised of several components whose operations are described in the following sections. 2.3.1.3 link multiplexer mode link multiplexer mode configures the mc92610 quad device into a dual transceiver. the transmit data interfaces for transmitters a and b are combined to form a 16-bit/20-bit, single data rate (sdr) interface. the data is sampled and stored on the rising edge of the transmit interface clock xmit_a_clk. the transmit data is aggregated and transmit out of link a. the outputs of link b are disabled. the transmit interface may also be operated in ddr mode by asserting ddre high. likewise, transmit data interfaces c and d are combined and transmit out of link c. transmit interface clock xmit_c_clk is used for transmitters c and d. the outputs of link d are disabled. table 2-2. transmitter control states xmit_ x _idle xmit_ x _k description ? low transmit data present on xmit_ x _7?xmit_ x _0 inputs. low high transmit idle (k28.5), ignore xmit_ x _7?xmit_ x _0 inputs. high high transmit control present on xmit_ x _7?xmit_ x _0 inputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 2. transmitter 2-7 functional description data on the transmitter a interface is sent first, followed by transmitter b. data on the transmitter c is sent first, followed by transmitter d. link multiplexer mode is enabled by asserting lme high. 2.3.1.4 repeater mode repeater mode configures the mc92610 into a 4-link receive-transmit repeater. in this mode, the data to transmit is obtained from its receiver (transmitter a gets receiver a?s data, transmitter b gets receiver b?s data, and so on). the transmit input signals, xmit_ x _7 - xmit_ x _0, xmit_ x _k and xmit_ x _idle are ignored. repeater mode is enabled by asserting repe high. see section 3.3.9 for more information on repeater mode. 2.3.1.5 transmit interface clock configuration the transmitter data interface operates at high frequency (up to 156.25mhz). in order to ease development of devices that interact with the mc92610, all of its data interfaces are source-synchronous. the data for each transmitter has its own dedicated clock input. this allows the clock at the source of the data to be routed with the data ensuring matched delay and timing. however, if per-transmitter clock sources are not available or deemed unnecessary, all transmitters may be clocked by a common clock source. this is enabled by asserting xmit_ref_a high. when xmit_ref_a is high, the xmit_a_clk becomes the interface clock for all active transmitters. the transmit interface clock inputs, xmit_ x _clk, and the pll reference clock, ref_clk_p/ref_clk_n, inputs must be operated at exactly the same frequency. however, there may be an arbitrary initial phase relationship between the pll reference clock and the transmit interface clocks. the phase relationship between the transmit interface clock and the pll reference clock is established after the internal pll locks. once locked, the transmit data interface tolerates + 180 o of transmit interface clock phase drift relative to the pll reference clock. additionally, all of the mc92610?s data interfaces are ddr, except in link multiplexer mode. ddr interfaces, in which the data is sampled and stored on the rising and falling edges of the clock, reduces the clock frequency by 50 percent while maintaining throughput. the configuration assertings of the mc92610 affect the legal range of clock frequencies at which it may be operated. section 4.1, table 4-1 shows legal transmit interface clock frequencies for all modes of operation. 2.3.1.6 8b/10b encoder operation the 8b/10b encoder encodes 8-bit data/control from the input register into 10-bit transmission characters . the ansi standard for fibre channel 8b/10b coding standard is followed [1,2]. running disparity is maintained and the appropriate transmission characters f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-8 mc92610 serdes user?s manual motorola functional description are produced, maintaining dc balance and sufficient transition density to allow reliable data recovery at the receiver. the inputs to the 8b/10b encoder are the data byte (xmit_ x _7-xmit_ x _0), special code signal (xmit_ x _k) and transmit idle signal (xmit _ x _idle ). data and legal control bytes are coded according to the 8b/10b method. illegal control bytes produce unpredictable transmission characters, leading to disparity and coding errors, ultimately reducing link reliability. the 8b/10b encoder produces an idle character (k28.5) of proper running disparity when xmit _ x _idle is low and xmit_ x _k is high, as indicated in table 2-2. the 8b/10b encoder is bypassed in tbi mode. 2.3.1.7 transmit driver operation the transmit driver drives transmission characters serially across the link. there are two transmit drivers per transmitter, the primary driver for outputs xlink_ x 0_p / xlink_ x 0_n, and the redundant driver for outputs xlink_ x 1_p / xlink_ x 1_n. each bit of coded data is transmitted differentially out of the enabled driver. the primary driver outputs, xlink_ x 0_p / xlink_ x 0_n, are enabled by asserting xcvr_ x _rsel low. the redundant driver outputs, xlink_ x 1_p / xlink_ x 1_n, are enabled by asserting xcvr_ x _rsel high. broadcast mode is enabled by asserting xmit_en_all high. in broadcast mode, all primary and redundant link outputs of all four transmitters are enabled, independent of the asserting the xcvr_ x _rsel signals. when xmit_en_all is low, only the selected link driver is active as described previously. both the primary and redundant link outputs are disabled when the transceiver is disabled by asserting xcvr_ x _disable high. 2.3.1.8 transmit equalization the transmit driver is a 50 ? controlled impedance driver. the media over which the signals are transmit, has high-frequency loss that contributes significantly to a distortion known as inter-symbol interference (isi). in order to offset, or equalize, the loss at high frequency, the mc92610?s transmit drivers provide additional gain at high frequencies. this is termed transmit equalization . transmit equalization has the greatest benefit when driving longer lengths of coax or when traversing across a large backplane. transmit equalization is of less benefit for short links. transmit equalization is enabled by asserting xmit_eq_en high. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 2. transmitter 2-9 functional description 2.3.1.9 loop-back test mode a special loop-back mode is supported for test. asserting lbe high enables loop-back mode causing the data being driven on the link outputs to be looped back to the input amplifier of the link?s receiver. loop-back data can be routed through either of the two output drivers. the path taken is controlled by the xcvr_ x _rsel signal. when xcvr_ x _rsel is low, data loops back through the primary driver (xlink_ x 0_p / xlink_ x 0_n), and when xcvr_ x _rsel is high, data loops back through the redundant driver (xlink_ x 1_p / xlink_ x 1_n). loop-back data is processed the same as normally received data. loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. the loop-back signals are electrically isolated from the link output signals. therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally. when in loop-back mode, the lboe signal controls the action of the link output signals. when lboe is low, the link outputs are undriven and are high-impedance. when lboe is high, the link output signals operate normally. lboe has no affect on the operation of the device when lbe is low. see section 5.2 for more information on system accessible test modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-10 mc92610 serdes user?s manual motorola functional description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-1 chapter 3 receiver this chapter describes the mc92610 receiver, its interfaces and operation. this chapter has the following sections: section 3.1, ?receiver block diagram? section 3.2, ?receiver interface signals? section 3.3, ?receiver functional description? the receiver takes a high speed differential serial data stream input, over samples it and recovers the data and clock, decodes it and presents it on a source synchronous parallel output data port. 3.1 receiver block diagram figure 3-1 shows a block diagram of the mc92610 receiver. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-2 mc92610 serdes user?s manual motorola receiver interface signals figure 3-1. mc92610 receiver block diagram 3.2 receiver interface signals this sections describes the interface signals of the mc92610 receiver. each signal is described, including its name, function, direction and active state in table 3-1. the table?s signal names use the letter ?x? as a place holder for the link identifier letter ?a? through recv_n_err recv_n_clk 8b/10b decoder ref_clk_n/p recv_n_[7:0] recv_n_k recv_n_idle rlink_n0_p rlink_n0_n wse recv_ref_a loop_back_data rx_clock multi-phase sampler transition tracking loop and data recovery idle detection and byte alignment bsync hse word alignment alignment fifo receiver interface recv_n_9 ddre bist/bert analyzer adie tst_0 tst_1 repeat_data repe drop_sync recv amp rlink_n1_p rlink_n1_n recv amp lme wsi wso rcce tbie recv_a_clk receive controller link_mux_data xcvr_n_rsel xcvr_n_disable recv_eq_en lbe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-3 receiver interface signals ?d.? internal signals are not available at the i/o of the device, but are presented to illustrate device operation. table 3-1. receiver interface signals signal name description function direction active state recv_ x _7 through recv_ x _0 received byte received and decoded data/control byte. the least significant 8 bits of received data in tbi mode. output - recv_ x _k special data indicator/ received bit 8 indicates that received byte is a special control byte. received bit 8 in tbi mode. errors are coded using this signal. see section 3.3.6.3 for error codes. output - recv_ x _9 received bit 9 received bit 9 in tbi mode. unused in 8-bit mode. output - recv_ x _idle receiver idle detect indicates that the receiver detected an idle character (operates in byte and tbi modes). errors are coded using this signal. see section 3.3.6.3 for error codes. output - recv_ x _err receiver error indicates that the receiver detected an error. recv_ x _idle and recv_ x _k must be decoded to determine error condition. see section 3.3.6.3 for error codes. output - recv_ x _clk receiver interface clock clock used for clocking receiver interface. source and frequency of this clock depend on operating mode. see section 4.1 for more information. output - drop_sync drop synchronization indicates that the current byte and word alignment should be invalidated and new alignment acquired. drop_sync is level sensitive and not synchronized to a clock, it must be asserted for at least two clock periods. input high xcvr_ x _disable transceiver disable indicates that the transmitter and receiver for this transceiver are disabled. input high xcvr_ x _rsel transceiver link select indicates that the redundant link inputs are observed and that primary link inputs are ignored. input high recv_eq_en receive equalization enable indicates that receiver equalization is enabled and that high frequency gain is applied to the received signal. input high tbie ten-bit interface enable indicates that the receiver interface is in ten-bit mode and that the 8b/10b decoder is bypassed. input high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-4 mc92610 serdes user?s manual motorola receiver interface signals hse half speed enable indicates to operate link at half-speed. both data and link interfaces run at half speed. input high lbe loop back enable activates digital loopback path, such that the loop-back data from the transmitter is accepted by the receiver. input high wse word synchronization enable indicates that all four receivers are being used in unison to receive synchronized data. input high wsi word synchronization bus input coded word synchronization bus input that is used to synchronize word timing between multiple mc92610 devices. see section 3.3.4.3 for multi-chip word synchronization operation. this signal should be tied high if multi-chip word synchronization is not being used. input - wso word synchronization bus output coded word synchronization bus output that is used to synchronize word timing between multiple mc92610 devices. see section 3.3.4.3 for multi-chip word synchronization operation. output - lme link multiplexer mode enable indicates that the data received on receiver a is presented 16/20 bits wide on parallel interfaces a and b. likewise, the data received on receiver c is presented 16/20 bits wide on parallel interfaces c and d. input high ddre double data rate enable when in link multiplexer mode (lme is high) this signal indicates that the data interfaces are running at double data rate. input high bsync byte alignment mode indicates that byte alignment is employed in the receiver. input high rcce recovered clock enable indicates that the clock frequency recovered by the receiver is used for the receiver interface clock (recv_ x _clk). otherwise, the reference clock frequency is used. this signal is used with the recv_ref_a signal to fully determine clock source. input high recv_ref_a receiver interface clock select indicates that the clock frequency recovered by receiver a is used as the receiver interface clock for all four receivers. this signal is used with the rcce signal to fully determine clock source. input high table 3-1. receiver interface signals (continued) signal name description function direction active state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-5 receiver functional description 3.3 receiver functional description the mc92610 receiver is based upon an oversampled transition tracking loop data recovery method. the receiver receives differential data in one of two operating ranges. it may be operated in full rate range with a maximum data rate of 2.5 gbps (3.125 gigabaud) or at half-rate at 1.25 gbps (1.5625 gigabaud). the operating range is determined by the state of the hse input. the received serial data is accumulated into ten-bit characters. the ten-bit characters are forwarded to the 8b/10b decoder where the original data is obtained. alternately, the decoder can be bypassed and the ten-bit character is forwarded to the receiver interface in ten-bit interface (tbi) mode. ref_clk_p/n pll reference clock pll input reference clock. provides reference frequency for the receiver interface when recovered clock mode is disabled (rcce is low). input - adie add/delete idle enable indicates that the receiver is free to add/delete idle characters to/from the output data stream to maintain alignment. input high repe repeater mode enable when enabled, the transmitter obtains transmit data from the receiver. input high tst_0/ tst_1 test mode indicates operating/test mode of the chip. input - rlink_ x 0_n/ rlink_ x 0_p link serial receive data, primary links differential serial receive data input pads for the primary links. input - rlink_ x 1_n/ rlink_ x 1_p link serial receive data, redundant links differential serial receive data input pads for the redundant links. input - internal signals rx_clock high speed transceiver clock internal, differential high speed clock used to transmit and receive link data. input - recv_a_clk receiver a interface clock internal copy of receiver a?s interface clock. input - loop_back_data loop back data differential loop back receive data. input - link_mux_data link multiplexer mode data received data from adjacent receiver to direct to receiver interface when in link multiplexer mode (lme is high.) input - repeat_data received repeat data repeater mode, received data to re-transmit. output - table 3-1. receiver interface signals (continued) signal name description function direction active state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-6 mc92610 serdes user?s manual motorola receiver functional description the receiver provides for byte (character) alignment. alignment assures that the byte as presented at the input of the transmitter is preserved when the byte is presented by the receiver. optionally, alignment may be disabled. the receiver also provides for word synchronization. in this mode, all of the receivers are being used cooperatively to receive 32-bit (40 bit in tbi mode) words. word synchronization assures that the receivers present the four bytes of a word simultaneously. the mc92610 also supports multi-chip word synchronization in which up to four mc92610 devices may be used to send and receive synchronized multi-words. the receiver has primary and redundant link inputs to support applications where redundancy is required. mc92610?s transition tracking loop has superior receive signal acquisition performance relative to pll-based clock and data recovery methods. this enables faster transition between the primary and redundant data streams. the receiver interface, where the received bytes and status codes are obtained, has several modes of operation and timing to allow it to be used in a variety of applications. the following sections provide a detailed description of the receiver and its modes of operation. 3.3.1 input amplifier the input amplifiers connect directly to the link input pads rlink_ x 0_p/n and rlink_ x 1_p/n. there are separate input amplifiers for the primary and redundant link inputs. the input amplifiers are differential with integrated analog multiplexer for loop-back testing. differential 100 ? link termination and in-line ac coupling capacitors are integrated with the amplifiers. note the integrated, in-line, ac coupling capacitors offer an extended common-mode input voltage range, however, compliance to the range as specified in section 6.2 is required for proper link operation. if a broader common-mode input voltage range is required then additional, off-chip, ac coupling capacitors must be used. the input amplifier facilitates a loop-back path for production and in-system testing. when the mc92610 is in loop-back mode (lbe set high), the input amplifier selects the loop-back differential input signals and ignores the state on the rlink_ x 0_p / rlink_ x 1_p and rlink_ x 0_n / rlink_ x 1_n signals. loop back data can be routed through either the primary or redundant input amplifier. the path taken is controlled by the xcvr_ x _rsel signal. when xcvr_ x _rsel is low, data loops back through the primary input amplifier, and when xcvr_ x _rsel is high, data loops back through the redundant input amplifier. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-7 receiver functional description loop-back data is processed the same as normally received data. loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. the loop-back signals are electrically isolated from the link input signals. therefore, if the inputs are shorted, open, or otherwise disturbed, the loop-back signals still operate normally. see section 5.2 for more information on system accessible test modes. 3.3.1.1 receiver equalization the media through which the signals are received, has high-frequency loss that contributes significantly to a distortion known as inter-symbol interference (isi). in order to offset, or equalize, the loss at high frequency, mc92610?s input amplifiers provide additional gain at high frequencies. this is termed receive equalization . receive equalization has the greatest benefit when receiving signals through longer lengths of coax or when traversing across a large backplane. receive equalization is of less-benefit for short links. receive equalization is enabled by asserting recv_eq_en high. the input amplifier facilitates a loop-back path for production and in-system testing. when the mc92610 is in loop-back mode (lbe set high), the input amplifier selects the loop-back differential input signals and ignores the state on the rlink_ x 0_p / rlink_ x 1_p and rlink_ x 0_n / rlink_ x 1_n signals. loop back data can be routed through either the primary or redundant input amplifier. the path taken is controlled by the xcvr_ x _rsel signal. when xcvr_ x _rsel is low, data loops back through the primary input amplifier, and when xcvr_ x _rsel is high, data loops back through the redundant input amplifier. loop-back data is processed the same as normally received data. loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. the loop-back signals are electrically isolated from the link input signals. therefore, if the inputs are shorted, open, or otherwise disturbed, the loop-back signals still operate normally. see section 5.2 for more information on system accessible test modes. 3.3.1.2 loop-back test mode the input amplifier facilitates a loop-back path for production and in-system testing. when the mc92610 is in loop-back mode (lbe set high), the input amplifier selects the loop-back differential input signals and ignores the state on the rlink_ x 0_p / rlink_ x 1_p and rlink_ x 0_n / rlink_ x 1_n signals. loop back data can be routed through either the primary or redundant input amplifier. the path taken is controlled by the xcvr_ x _rsel signal. when xcvr_ x _rsel is low, data loops back through the primary input amplifier, and when xcvr_ x _rsel is high, data loops back through the redundant input amplifier. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-8 mc92610 serdes user?s manual motorola receiver functional description loop-back data is processed the same as normally received data. loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. the loop-back signals are electrically isolated from the link input signals. therefore, if the inputs are shorted, open, or otherwise disturbed, the loop-back signals still operate normally. see section 5.2 for more information on system accessible test modes. 3.3.2 transition tracking loop and data recovery the received differential data from the input amplifier is sent to the transition tracking loop for data recovery. the mc92610 uses an oversampled transition tracking loop method for data recovery. the differentially received data is sampled and processed digitally providing for low bit error rate (better than 10 -12 ) data recovery of a distorted bit stream. the transition tracking loop is tolerant of frequency offset between the transmitter and receiver. the mc92610 reliably operates with + 100 ppm of frequency offset. the transition tracking loop synthesizes a recovered clock that matches the frequency of the received data. recovered data is accumulated into 10-bit characters. characters are aligned to their original 10-bit boundaries if a byte alignment mode is enabled. 3.3.3 byte alignment the receiver supports the alignment of accumulated bits to their original transmitted character boundaries through idle character recognition. byte alignment is supported in byte and tbi interface modes. byte alignment is enabled by asserting bsync high. 3.3.3.1 byte alignment and realignment method at power-up, the receiver starts an alignment procedure, searching for the 10-bit pattern defined by the 8b/10b idle code. alignment logic checks for the distinct idle pattern, ?0011111 010? and ?1100000101? (ordered bit 0 to bit 9), characteristic of the k28.5 idle pattern. the search is done on the 10-bit data in the receiver, and is therefore independent being in byte or tbi mode. alignment requires a minimum of four, error-free, received idle characters to ensure proper alignment and lock. non-idle characters may be interspersed with the idle characters. the disparity of the idle characters is not important to alignment and can be positive, negative or any combination. the receiver begins data flow of received characters once alignment is established and locked. however, if word synchronization is enabled, received characters do not flow to the receiver interface until word synchronization is established. alignment remains locked until any one of three events occur that indicate loss of alignment: alignment is lost when a misaligned idle sequence is detected. a misaligned idle sequence is defined as four idle characters with an alignment different than the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-9 receiver functional description current alignment. non-idle characters may be dispersed between the four misaligned idles, however, a properly aligned idle character breaks the sequence. alignment is automatically changed to the newly detected alignment without halting data flow. alignment is lost when the number of received characters with 8b/10b coding errors outnumbers the non-errored characters by four. credit for non-errored characters in excess of errored characters is limited to four, such that alignment is lost after four consecutive errored characters. misalignment detection of this type is not available in tbi mode. the receiver restarts its alignment procedure and halts data flow until a new alignment is established. alignment is lost when the drop_sync input is set high for at least two clock periods. current alignment is invalidated, the receiver restarts its alignment procedure and halts data flow until a new alignment is established. drop_sync is level-sensitive and asynchronous. when establishing byte alignment, or when data flow is interrupted due to misalignment, the receiver?s recv_ x _err signal is high and the ?not byte sync? error is reported as described in section 3.3.6.3. note during the power up sequence the receiver interface may have indeterminate data present and the recv_ x _clk is disabled. when pll lock is established the recv_ x _clk becomes active and the receiver interface output data is forced to a negative running k28.5 character (0x17c on bits 9, k, data[7:0]) until a byte-sync is established. 3.3.3.2 non-aligned method no attempt is made to align the incoming data stream when bsync is low. the bits are simply accumulated into 10-bit characters and forwarded. this mode should be used only with tbi mode, tbie set high, and with word synchronization disabled, wse set low. at system reset and until the mc92610?s system pll is locked to its reference, the receiver?s recv_ x _err signal is high and the ?not byte sync? error is reported, as described in section 3.3.6.3. this may seem confusing because no byte synchronization is performed; but in this mode the status simply indicates that the system pll has not achieved lock. 3.3.4 word synchronization the four receivers in the mc92610 can be used cooperatively to receive 32-bit wide aligned word transfers. word synchronization is enabled by asserting wse high. multiple f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-10 mc92610 serdes user?s manual motorola receiver functional description mc92610 devices may be used to receive multi-word aligned transfers, through the use of the word synchronization bus interface. word synchronization is possible in byte or tbi mode. however, word synchronization is dependent on the detection of simultaneously transmitted word synchronization events that contain idle characters. therefore, if operating in tbi mode, the idle character must be a supported member of the code set. 3.3.4.1 word synchronization method word synchronization aligns characters in the receiver?s alignment fifo. synchronization is accomplished by lining up word synchronization events detected by each of the receivers, such that all are coincident at the same stage of their fifo. a word synchronization event is defined as four consecutive non-errored idle (k28.5) characters followed by at least one non-idle character. word synchronization events must be generated at all concerned transmitters simultaneously in order for synchronization to be achieved. word synchronization events must be received at all receivers within 40 bit-times of each other. word synchronization is not attempted until all receivers are byte align locked. word synchronization events are used to establish a relationship between the received bytes in each of the receivers. the bytes of a word are matched and presented simultaneously at the receiver interface. once synchronization is achieved the receiver tolerates + 6 bit-times of drift between receivers. if drift exceeds + 6 bit-times the receiver will continue to operate. however, the received bytes will no longer be synchronized properly because the receiver remains locked on the initially established synchronization. word synchronization remains locked until any one of the following three events occur that indicate loss of synchronization: word synchronization lock is lost when one or more of the receivers lose or change byte alignment. byte alignment loss is described in section 3.3.3.1. word synchronization lock is lost when overrun/underrun is detected on one or more of the receivers, see section 3.3.6.3 for more about overrun/underrun. word synchronization lock is lost when explicitly invalidated by asserting drop_sync high for at least two clocks. when lock is lost, word synchronization must be re-established before data flow through the receiver resumes. the receiver interface is disabled during word synchronization. no data is produced at its outputs until word synchronization is achieved and the first non-idle character is received. when establishing word synchronization, or when word synchronization is lost, the receiver?s recv_ x _err signal is high and the ?not word sync? error is reported as described in section 3.3.6.3. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-11 receiver functional description for further details on how the receiver interface is disabled during initial word synchronization see the note at the end of section 3.3.3.1, ?byte alignment and realignment method,? on page 3-8. 3.3.4.2 word synchronization bus word synchronization information and timing are communicated across the word synchronization bus. the wso output drives the bus that is connected to the wsi inputs of other mc92610 devices with which word synchronization is desired. one of the mc92610 devices is connected as the leader and the others as the followers. the leader?s wso output is used to drive its own wsi input and the wsi inputs of all of the followers. the wso output of the follower devices is not used and is not connected. note in order for word synchronization to operate properly in applications where only one mc92610 is used, the wsi input must be tied high. 3.3.4.3 multi-chip word synchronization up to four mc92610 devices may be connected to perform multi-word synchronized data transfer. configurations of one, two, three and four devices are possible supporting 32-bit, 64-bit, 96-bit and 128-bit wide data transfers. one of the mc92610 devices is connected as the leader and the others as the followers as described in section 3.3.4.2. multi-chip word synchronization uses the same mechanisms for word synchronization as single-chip word synchronization as described in section 3.3.4.1. word synchronization events must be generated at all concerned transmitters simultaneously in order for synchronization to be achieved. word synchronization events must be received at all receivers within 40 bit-times of each other. when the leader device detects a word synchronization event at its receivers, it communicates the timing of the event to the follower devices through the word synchronization bus. the follower devices use this timing to establish their own word synchronization relative to the leader. once synchronization is achieved, + 6 bit-times of drift between all of the devices? receivers is tolerated. if drift exceeds + 6 bit-times the devices will continue to operate. however, the devices will no longer be synchronized properly because they remain locked on the initially established synchronization. if any of the devices lose word synchronization, as described in section 3.3.4.1, all of the receiving devices must be forced to lose synchronization to ensure proper resynchronization. therefore, system logic should detect loss of word synchronization on all of the devices by decoding the ?not word sync? error. then the drop_sync should f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-12 mc92610 serdes user?s manual motorola receiver functional description be set high for at least two clock cycles and then released to force all devices to re-establish word synchronization. 3.3.4.4 recommended mode states for word synchronization word synchronization can only be used with certain operating modes and has limited application in others. table 3-2 describes the relationship between modes and word synchronization. table 3-2. word synchronization states mode signals recommended state description word synchronization wse high enables word synchronization. byte synchronization bsync high word synchronization depends upon idle character detection. byte alignment is required for idle detection. add/delete idle adie high when enabled, allows the receiver to add/delete idle patterns in order to maintain word alignment. this is the recommended operating mode when the reference clock is being used to time the receiver interface (rcce set low) and there is a frequency offset between the transmitter and receiver. idles are added or dropped to maintain word alignment. recovered clock rcce low the receiver interface must be timed with the reference clock when utilizing multi-chip word synchronization. timing errors will occur on the word synchronization bus if rcce is high. if utilizing single chip word synchronization, then either the recovered clock or the reference clock may be used to time the receiver interface. rcce may be set as it best suites the application. receiver interface clock select recv_ref_a high if utilizing single chip word synchronization and using the recovered clock (rcce set high) then receiver a?s recovered clock must be used for all receivers. the data at the receiver interfaces will be skewed if the individual receiver recovered clocks (recv_ref_a set low) are used to time the receiver interfaces. transceiver disable xcvr_ x _disable low all four transceivers must be enabled for word synchronization. repeater mode repe low word synchronization is not recommended in repeater mode. ten-bit interface tbie n/a when enabled, the idle character must be part of the tbi code set. when disabled, the idle is naturally supported by the 8b/10b codes. link multiplexer mode lme n/a word synchronization operates normally in link multiplexer mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-13 receiver functional description 3.3.5 8b/10b decoder the 8b/10b decoder takes the 10-bit character from the transition tracking loop and decodes it according to the 8b/10b coding standard [1,2]. the decoder does two types of error checking. first it checks that all characters are a legal member of the 8b/10b coding space. the decoder also checks for running disparity errors. if the running disparity exceeds the limits set in the 8b/10b coding standard then a disparity error is generated. note 8b/10b coding is meant only to improve data transmission characteristics and is not a good error detection code. many 8b/10b characters alias to other valid 8b/10b characters in the presence of bit errors. error detection and correction techniques must be applied outside of mc92610 if better than 10 -12 bit error rate is required. an illegal character or disparity error sets the recv_ x _err signal high, coincident with the received data for one byte output period. the ?code error? or ?disparity error? is reported as described in section 3.3.6.3. it is difficult to determine the exact byte that causes a disparity error, so the error should not be associated with a particular received byte. it is rather a general indicator of the improper operation of the link. its intended use is for the system to monitor link reliability. the 8b/10b decoder is bypassed when operating in tbi mode (tbie set high.) 3.3.6 receiver interface the receiver interface facilitates transfer of received data to the system. it also provides information on the status of the link. table 3-1 describes each of the signals involved in receiver operation. the receiver interface, through which received data is obtained, may be operated in byte mode or in tbi mode. there are several timing mode options for the receiver interface. each of the operating modes are described below. half-speed enable hse n/a does not affect word synchronization. double data rate ddre n/a does not affect word synchronization. table 3-2. word synchronization states (continued) mode signals recommended state description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-14 mc92610 serdes user?s manual motorola receiver functional description 3.3.6.1 byte interface byte interface mode is enabled by setting tbie low. received data is a byte (8 bits) of uncoded data when in byte mode. the internal 8b/10b decoder is used to decode data from the 10-bit character received. the received byte is on the recv_ x _7?recv_ x _0 signals. the recv_ x _k is high when the byte represents a special 8b/10b code, otherwise it is low, indicating that the byte is normal data. the recv_ x _idle is high when the byte is the special 8b/10b idle (k28.5) code. this can be used by system logic for synchronization or data parsing. recv_ x _idle is low when the byte is normal data or a non-idle special code. recv_ x _idle is high and recv_ x _k is low to indicate that an underrun/overrun error occurred. see section 3.3.6.3 for more information on error conditions. the recv_ x _err is low when the receiver is operating normally, and is high when received data contains an error or the receiver is in an error state. the state of the recv_ x _idle and recv_ x _k signals are decoded to determine the error condition. table 3-3 describes the error codes and their meaning. 3.3.6.2 ten-bit interface ten-bit interface mode is enabled by setting tbie high. received data is ten-bits of pre-coded data when in tbi mode. the internal 8b/10b decoder is not used and it is assumed that decoding is done externally. ten-bit data is the collection of signals: recv_ x _9, recv_ x _k, and recv_ x _7?recv_ x _0 making up bits 9 through 0, respectively. the recv_ x _idle is high when the 10-bit character is the special 8b/10b idle (k28.5) code. this can be used by system logic for synchronization or data parsing. recv_ x _idle is low when the data is normal data or a non-idle special code. the recv_ x _err is low when the receiver is operating normally, and is high when the receiver is in an error state. the state of the recv_ x _idle signal is decoded to determine the error condition. table 3-4 describes the error codes and their meaning. 3.3.6.3 receiver interface error codes the receiver?s status and data error conditions are coded on the recv_ x _err, recv_ x _idle and recv_ x _k signals. when recv_ x _err is low, the receiver is operating normally and no error conditions exist (with exception of underrun/overrun error in byte mode.) when recv_ x _err is high, the data on the receiver?s output is questionable due to an error condition or lack of synchronization. initially, recv_ x _err is high indicating that the receiver is in one of its start-up phases. table 3-3 describes the error conditions and their signal coding for byte mode. table 3-4 describes the error conditions and their signal coding for tbi mode. the priority column in the tables show f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-15 receiver functional description the error reported if multiple errors occur at the same time. the lower the priority numbered errors are reported first. 3.3.7 receiver interface clock timing modes the receiver interface is double data rate, source synchronous. each of the receiver?s eleven output signals (eleven for byte interface and twelve for ten-bit interface) are timed relative to the rising and falling edges of the receiver interface clock output, recv_ x _clk. the receiver interface clock frequency may be selected between its own recovered clock frequency, receiver a?s recovered clock frequency, or the frequency of the reference clock input(s) ref_clk_p / ref_clk_n. the recovered clock enable signal, rcce, determines if the receiver interface is timed to the recovered clock or to the local reference clock. asserting rcce enables timing relative to the recovered clock, and set low enables timing relative to the reference clock. when table 3-3. receiver interface error codes (byte interface) recv_ x _err recv_ x _k recv_ x _idle priority description low low low 8 normal operation, valid data character received. low low high 3 overrun / underrun: the receiver interface synchronization logic detected an overrun/underrun condition. data may be dropped or repeated. low high low 7 normal operation, valid control character received. low high high 6 normal operation, valid idle (k28.5) character received. high low low 4 code error: the 8b/10b decoder detected an illegal character. high low high 5 disparity error: the 8b/10b decoder detected a disparity error. high high low 1 not byte sync: the receiver is in start-up or has lost byte alignment and is searching for alignment. high high high 2 not word sync: the receiver is byte synchronized but has not achieved or has lost word alignment and is searching for alignment. table 3-4. receiver interface error codes (ten-bit interface) recv_ x _err recv_ x _idle priority description low low 4 normal operation, non-idle character received. low high 3 normal operation, idle (k28.5) character received. high low 1 not byte/word sync: the receiver is in start-up or has lost byte or word alignment and is searching for alignment. high high 2 overrun/underrun: the receiver interface synchronization logic detected and overrun/underrun condition. data may be dropped or repeated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-16 mc92610 serdes user?s manual motorola receiver functional description rcce is asserted high, then the signal recv_ref_a is used to select the recovered clock to be used. if recv_ref_a is asserted then channel a?s recovered clock is used for all four channels. if it is low then each channel uses its own recovered clock. the receiver interface clock signals, recv_ x _clk, will always be present when the pll is in lock. this is true even if there is no signal present on the serial inputs or if the receiver has not achieved alignment or byte sync. the frequency of the receiver clock will be the local reference clock. the clock signals however, are not present during power up or when the mc92610 is in reset mode and the pll is not locked. 3.3.7.1recovered clock timing mode with rcce asserted, the recovered clock signal, recv_ x _clk, is generated by the receiver and, on average, runs at the reference clock frequency of the transmitter at the other end of the link. the recovered clock is not generated by a clock recovery pll, but is generated by the receiver bit-accumulation and byte-alignment logic. in order to track a transmitter frequency that is offset from the receiver?s reference clock frequency, the duty cycle and period of the recovered clock is modulated. the mc92610 is designed to tolerate up to a 200 ppm of frequency offset. the recovered clock duty cycle may be reduced or increased (by 200 ps, if the nominal frequency is 156.25 mhz) in order to match the transmitter frequency. for example: if the transmitter is sending data at a rate faster than the receiver, then a shortened cycle is generated as needed to track the incoming data rate. alternately, if the transmitter is running slower than the receiver, then a long cycle is generated. all receiver channel outputs are source synchronous with their respective recv_ x _clk outputs. if the receivers are being operated in word synchronization mode (wse = high), the data for all four receivers are timed relative to link a?s recovered clock recv_a_clk. in word synchronization all four clocks are derived from channel a and may be used if necessary. 3.3.7.2 reference clock timing mode data is timed relative to the local reference clock frequency when rcce is low. synchronization between the recovered clock and the reference clock is handled by the receiver interface. frequency offset between the transmitter?s reference clock and the receiver?s reference clock causes overrun/underrun situations. overrun occurs when the transmitter is running faster than the receiver. underrun occurs when the transmitter is running slower than the receiver. in an overrun situation, a byte of data needs to be dropped in order to maintain synchronization between the clock domains. the receiver interface searches for an idle byte to drop when overrun is imminent. however, the idle is dropped only if add/delete idle (adi) mode is enabled by asserting adie. when enabled, idle patterns are dropped to f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 3. receiver 3-17 receiver functional description maintain synchronization. if sufficient idle patterns are not available to drop, receiver overrun may occur. when overrun occurs, the ?overrun/underrun? error is reported as described in section 3.3.6.3, ?receiver interface error codes,? for one byte clock period. an overrun error is also reported if adi mode is disabled and overrun occurs, even if idles are available to drop. a sufficient number of idles must be transmitted to guard against overrun. the frequency of idles can be computed based upon the maximum frequency offset between transmitter and receiver in the system. the number of bytes (characters) that can be transmitted between idles is: (10 6 / n) - 1 bytes where: n is the frequency offset in ppm. in an underrun situation, a byte of data needs to be added in order to maintain synchronization between the clock domains. the receiver interface adds an idle byte when underrun is imminent. however, the idle is added only if add/delete idle (adi) mode is enabled by asserting adie. if adi mode is disabled and underrun occurs, the ?overrun/ underrun? error is reported as described in section 3.3.6.3, ?receiver interface error codes,? for a one byte clock period. 3.3.8 half-speed mode half speed (hs) mode, enabled when hse is high, operates the receiver in its lower speed range. in hs mode, the link speed is 1.25 gbps (1.5625 gigabaud.) the receiver interface operates at half speed as well, in pace with received data. 3.3.9 repeater mode repeater mode configures the mc92610 quad device into a 4-link receive-transmit repeater. in this mode, received data is forwarded to the transmitter for re-transmission. link a?s receiver forwards to link a?s transmitter, link b?s receiver to link b?s transmitter and so on. the receiver?s data outputs and status signals reflect the received data and the current status of the receiver. see section 2.3.1.4 for more information on repeater mode. 3.3.10 link multiplexer mode link multiplexer mode configures the mc92610 quad device into a dual transceiver. the link multiplexer mode is enabled by asserting lme high. receivers a and c are active and are used to receive data. the input circuitry to receivers b and d are disabled and inactive. the advantage of this mode is that data from a single receiver is demultiplexed onto two receiver interfaces. their single data rate (sdr) operation allows full speed link operation while lowering the parallel interface speeds by one-half. data from receiver a is presented on receiver interfaces a and b. once byte synchronization is achieved, the first non-idle character received is output on receiver f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-18 mc92610 serdes user?s manual motorola receiver functional description interface a, the second on receiver interface b. it is recommended that idles be transmitted simultaneously as a and b pairs. if idles are transmitted on only one input byte, they must be on b to maintain the proper byte order in the 16 bit output. the link status codes on receiver interface a and b represent the status of the current character. both sets of status signals are active and must be observed. the received data is timed relative to the rising edge of the receiver interface clock, recv_ x _clk. the receive interface may also be operated in ddr mode by asserting ddre high. link multiplexer mode is enabled by asserting lme high. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 4. system design considerations 4-1 chapter 4 system design considerations this chapter describes the system design considerations for the mc92610, including clock configuration, device startup and initialization, and proper use of repeater mode. 4.1 reference clock configuration the clock inputs ref_clk_p and ref_clk_n are the differential reference clock inputs for the mc92610. the frequency of the clock signal applied to these inputs along with the settings on the configuration inputs determine the speed at which the serial links operate. also, the legal ranges of reference clock frequencies vary depending on the configuration selected. table 4-1 shows the ranges allowed for each configuration. note the device must be reset by setting reset low, if the reference clock configuration is changed after power-up. the clock inputs ref_clk_p and ref_clk_n are normally driven with a differential clock source. however, the reference clock may also be driven with a single-ended source. in this situation, the ref_clk_p signal is driven by the single-ended clock source and the ref_clk_n signal is held at the hstl reference voltage as defined in section 6.2. the table 4-1. legal reference clock frequency ranges hse lme ddre reference frequency min (mhz) reference frequency max (mhz) link transfer rate (gigabaud) low low low reserved reserved reserved low low high 95.00 156.25 1.900 - 3.125 low high low 95.00 156.25 1.900 - 3.125 low high high 47.50 78.125 1.900 - 3.125 high low low reserved reserved reserved high low high 47.50 78.125 0.950 - 1.5625 high high low 47.50 78.125 0.950 - 1.5625 high high high 23.75 39.0625 0.950 - 1.5625 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-2 mc92610 serdes user?s manual motorola startup ref_clk_n signal may be connected to its own reference voltage circuit or may share the reference voltage circuit used for the hstl_vref signal, if board layout allows. 4.2 startup the mc92610 begins a startup sequence upon application of the reference clock (ref_clk_n/p input) to the device. this is considered a cold startup. the cold startup sequence is as follows: 1. pll startup 2. receiver initialization and byte alignment 3. word alignment (if enabled) 4. run the expected duration of each step in the startup sequence is shown in table 4-2. a cold startup can be initiated at any time by setting reset low. it is recommended that reset be low at initial startup, however, it is not strictly required. 4.3 repeater mode the mc92610 may be configured into a four-link receive-transmit repeater by setting repe high. in repeater mode data received on link a's receiver is forwarded to link a's transmitter, link b's receiver to link b's transmitter and so on. the configuration inputs may be used to control how the repeater handles the data as it passes through the repeater. certain configurations are more effective than others for various applications. the transmitter at the source, the receiver at the destination and the repeater must have compatible configurations to ensure proper operation. the following sections describe how each configuration control affects repeater operation. 4.3.1 ten-bit interface mode when the device is in tbi mode (tbie set high) the internal 8b/10b encoder and decoder are bypassed and the ten-bit data received is forwarded directly to the transmitter. running disparity is assumed correct and is not checked. this is important when using disparity based word synchronization where incorrect running disparity is used as a word table 4-2. startup sequence step duration startup step typical duration (in bit times) note pll startup 20,480 + 25 s receiver initialization 300 wse = low 460 wse = high word alignment 160 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 4. system design considerations 4-3 repeater mode synchronization event marker. ten-bit mode must be enabled for disparity based word alignment to operate properly because it allows the improper disparity to pass through the repeater. when byte interface mode is enabled (tbie set low) received data is passed through the 8b/10b decoder where it is converted into its eight-bit data or control byte. running disparity and code validity are checked and reported with the received byte at the receiver interface as described in section 3.3. the decoded byte is re-coded by the transmitter?s 8b/10b encoder for transmission. note byte interface mode must not be used with non-aligned mode. 4.3.2 byte alignment mode the byte alignment may be used in repeater mode as long as ten-bit interface mode is not also being used. when establishing byte alignment for the link through the repeater, the byte alignment sequence must be repeated twice, once for the repeater and once for the destination?s receiver. for example, at least eight idle characters must be transmit, four for repeater alignment and four for the destination?s receiver alignment. 4.3.3 word synchronization mode word synchronization may be used in repeater mode. this allows the incoming bytes to be synchronized into their corresponding words, removing cable skew from the transmission source and re-establishing synchronization. similar to byte alignment, the word synchronization sequence must be repeated twice, once for the repeater and once for destination?s receiver. for example, a 4 idle/1 non-idle word synchronization event must be transmit followed by a second 4 idle/1 non-idle word synchronization event to enable the entire link to establish word synchronization. of course, byte alignment must be established, as described in section 4.3.2, prior to word synchronization. 4.3.4 recovered clock timing mode the mc92610?s four transmitters are timed exclusively to the reference clock domain. recovered clock mode cannot be used in repeater mode. the setting on the recovered clock enable input, rcce, is ignored when in repeater mode and all data is timed to the reference clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-4 mc92610 serdes user?s manual motorola configuration and control signals 4.3.5 reference clock timing mode repeater mode is timed exclusively to the reference clock domain as stated above. a frequency offset between the source transmitter and the repeater will cause the repeater?s receiver to eventually overrun/underrun. to ensure that overrun/underrun does not cause data to be lost, add/drop idle mode must be used. add/drop idle mode is enabled by setting adie high. the repeater adds or drops idles from the data stream to maintain alignment to the reference clock. the guidelines for idle density are discussed in section 4.3.2. 4.3.6 half-speed mode, double data rate mode half-speed mode and double data rate mode simply affect the frequency of the reference clock that must be provided and the timing of the receiver interface. all combinations of these modes are supported in repeater mode. see section 3.3.8 for more information on half-speed mode and section 3.3.6 for more information on double data rate mode. 4.4 configuration and control signals mc92610 has many configuration and control signals that are asynchronous to all inputs clocks. most of the signals affect internal configuration state and must be set at power-up. if their state is changed after power-up, some require that the chip be reset by setting reset_b low and then releasing high. while other configuration signals are meant to be changed during normal operation and do not require chip reset. however, these signals may still affect device operation. table 4-3 lists all of the mc92610?s asynchronous configuration and control signals and describes the effect of changing their state after power up. table 4-3. asynchronous configuration and control signals signal name description effect of changed state xcvr_ x _rsel transceiver redundant link select receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. xcvr_ x _disable transceiver disable receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. drop_sync drop synchronization receiver must re-establish byte and word synchronization. xmit_ref_a transmitter reference clock a select device must be reset. recv_ref_a receiver reference clock a select device must be reset. xmit_eq_en transmitter equalization enable may cause short burst of bit errors. recv_eq_en receiver equalization enable may cause short burst of bit errors. xmit_en_all transmitter enable, all outputs no action required. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 4. system design considerations 4-5 power supply requirements 4.5 power supply requirements the recommended board for the mc92610 has a minimum of two solid planes of one ounce copper. one plane is to be used as a ground plane and the second plane is to be used for the 1.8v supply. it is recommended that the board has its own 1.8v and 1.5v regulators with less than 50mv ripple. 4.6 phase locked loop (pll) power supply filtering an analog power supply is required. the tx_pllvdd signal provides power for the analog portions of the pll. to ensure stability of the internal clock, the power supplied to the pll is filtered using a circuit similar to the one shown in figure 4-1. for maximum effectiveness, the filter circuit is placed as close as possible to the tx_pllvdd ball to ensure it filters out as much noise as possible. the ground connection should be near the tx_pllvdd ball. the 0.003mf capacitor is closest to the ball, followed by the 1 mf capacitor, and finally the 1 w resistor to vdd on the 1.8v power plane. the capacitors are connected from tx_pllvdd to the ground plane. use ceramic chip capacitors with the highest possible self-resonant frequency. all traces should be kept short, wide and direct. tbie ten-bit interface enable device must be reset. hse half-speed enable device must be reset. ddre double data rate enable device must be reset. bsync byte synchronization mode device must be reset. adie add/drop idle enable device must be reset. repe repeater mode enable device must be reset. lme link multiplexer mode device must be reset. rcce recovered clock enable device must be reset. wse word synchronization enable device must be reset. lbe loop back enable receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. lboe loop back output enable no action required. reset system reset bar device is reset. table 4-3. asynchronous configuration and control signals (continued) signal name description effect of changed state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-6 mc92610 serdes user?s manual motorola power supply decoupling recommendations figure 4-1. pll power supply filter circuits 4.7 power supply decoupling recommendations the mc92610 requires a clean, tightly regulated source of power to ensure low jitter on transmit, and reliable recovery of data in the receiver. an appropriate decoupling scheme is outlined below. only surface mount technology (smt) capacitors should be used, to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. first, the board should have about 10 x 10nf smt ceramic chip capacitors as close as possible to the 1.8v (vdd and xvdd) balls of the device. the board should also have about 10 x 10nf smt ceramic chip capacitors as close as possible to the 1.5v (v ddq ) balls of the device. where the board has blind vias, these capacitors should be placed directly below the mc92610 supply and ground connections. where the board does not have blind vias, these capacitors should be placed in a ring around the mc92610, as close to the supply and ground connections as possible. second, there should be a 1uf ceramic chip capacitor on each side of the mc92610 device. this should be done for both the 1.8v supply and the 1.5v supply. third, between the mc92610 device and the voltage regulator, there should be a 10uf, low equivalent series resistance (esr) smt tantalum chip capacitor, and a 100uf, low esr smt tantalum chip capacitor. this should be done for both the 1.8v supply and the 1.5v supply. 4.8 hstl reference voltage recommendation the mc92610 uses hstl class-i inputs and outputs for all of its high-frequency parallel interface signals. the hstl class-i interfaces are compatible with the eia/jedec standard eia/jesd8-6 [3]. hstl class-i inputs define their switching thresholds about a reference voltage supplied at an input of the device. the reference voltage is applied to the hstl_vref input of the mc92610. the reference voltage, referred to as v ref in table 6-3, must fall within the v dd 1 ? 0.003 f tx_pllv dd 1.0 f gnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 4. system design considerations 4-7 impedance control reference recommendation minimum and maximum voltages as specified and must have no more than 2 percent peak-to-peak ac noise. in practice, v ref for the hstl inputs should track the variations in the dc value of v ddq of the sending device for best noise margin. the value of v ref is to be selected by the user to provide optimum noise margin. figure 4-2 shows a recommended circuit topology to generate v ref with recommended ceramic chip filter capacitor. 4.8.1 voltage reference for single-ended reference clock use the differential reference clock inputs, ref_clk_p/n, may also be driven by a single-ended source as described in section 4.1. the ref_clk_n input must be set at vref for single-ended operation of ref_clk_p. the ref_clk_n signal may be connected to its own reference voltage circuit or may share the reference voltage circuit used for the hstl_vref signal, if board layout allows. 4.9 impedance control reference recommendation the mc92610 has an integrated active impedance calibration circuit to ensure the best possible impedance control of the receiver?s link termination resistors. the calibration circuit uses an externally established impedance against which internal impedance is calibrated. the user connects a 250 ? , 1percent tolerance, resistor between the mc92610 z_calib input and ground. the z_calib input may be tied to gnd to disable impedance calibration, or may be tied to vdd which will set the input impedance to its maximum value. figure 4-3 shows an example impedance reference circuit topology. figure 4-2. hstl class-i v ref circuit v ddq gnd gnd 1.0 f hstl_v ref 100 ? 110 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-8 mc92610 serdes user?s manual motorola impedance control reference recommendation figure 4-3. impedance reference circuit gnd z_calib 250 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 5. test features 5-1 chapter 5 test features the mc92610 supports several test modes for in-system bist and production testing. the mc92610 also has an ieee std. 1149.1 [4] compliant test access port and boundary scan architecture implementations. this chapter covers the jtag implementation and the system accessible test modes. 5.1 ieee std. 1149.1 implementation this section describes the ieee std. 1149.1 compliant test access port and boundary scan architecture implementation in the mc92610. note there are no internal pull-ups/pull-downs on any jtag input. this is an exception to the ieee std. 1149.1 standard. the inputs should be properly terminated externally. 5.1.1 test access port (tap) interface signals table 5-1 lists the interface signals for the tap. table 5-1. tap interface signals signal name description function direction active state tck test clock test logic clock. input - tms test mode select tap mode control input. input - tdi test data in serial test instruction/data input. input - trst test reset bar asynchronous test controller reset. input low tdo test data out serial test instruction/data output. output - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-2 mc92610 serdes user?s manual motorola ieee std. 1149.1 implementation note if trst is not held low during power-up or does not receive an active low reset after power-up, the test logic may assume an indeterminate state disabling some of the normal transceiver functions. it is recommended that trst be terminated in one of the following manners. 1. trst be driven by a tap controller that provides a reset after power-up. 2. connect trst to reset. 3. terminate trst with a 1k ohm resistor (or hard wire) to ground. 5.1.2 instruction register is the 5.1.3 instructions table 5-2 lists the public instructions provided in the implementation and their instruction codes. table 5-3 lists the private instruction codes that if executed could be hazardous to device operation. the user should not execute these instructions. bit position 43210 field ir capture-ir value00001 figure 5-1. instruction register table 5-2. tap controller public instructions instruction code enabled serial test data path bypass 11111 bypass register clamp 01100 bypass register extest 00000 boundary scan register highz 01001 bypass register idcode 00001 id register sample 00010 boundary scan register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 5. test features 5-3 system accessible test modes 5.1.4 boundary-scan register a full description of the boundary scan register may be found in the bsdl file provided by motorola upon request. 5.1.5 device identification register (0x0280e01d) 5.1.6 performance the performance and electrical properties of the tap controller, boundary scan, and jtag inputs and outputs are described in chapter 6, ?electrical specifications and characteristics. 5.2 system accessible test modes system accessible test modes are selected through the tst_0, tst_1 and lbe signals. table 5-4 shows test mode state selection. . table 5-3. tap controller private instruction codes instruction code instruction code 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 - 31 28 27 12 11 0 field version part number manufacturer id value00000010100000001110000000011101 figure 5-2. device identification register table 5-4. test mode state selection tst_1 tst_0 lbe description low low low normal operation. no test mode enabled. low low high loop back system test mode. low high low bist sequence system test mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-4 mc92610 serdes user?s manual motorola system accessible test modes 5.2.1 loop back system test the mc92610 can be configured in loop back mode where the transmitted data is looped back to its receiver independent of the receiver?s link inputs. this is enabled by setting lbe high. the characters transmitted are controlled by the normal transmitter controls. if the transceiver is working properly, the data/control characters transmitted are received by the receiver. this allows system logic to use various data sequences to test the operation of the transceiver. the data is looped back though the primary link path if xcvr_ x _rsel is low and through the redundant path if xcvr_ x _rsel is high. the loop-back signals are electrically isolated from the xlink0/1_ x _p or xlink0/1_ x _n output signals. therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally. when in loop-back mode, the lboe signal controls the action of the selected link output signals. when lboe is low, the xlink0_ x _p / xlink1_ x _p or xlink0_ x _n / xlink1_ x _noutput signals are undriven and are high-impedance. when lboe is high, the link output signals enabled by xcvr_ x _rsel continue to operate normally. the receiver?s link input signals, rlink0_ x _p / rlink1_ x _p and rlink0_ x _n / rlink1_ x _n, are electrically isolated during loop back mode, such that their state does not affect the loop back path. 5.2.2 bist sequence system test mode the mc92610?s transmitter has an integrated, 23rd order, pseudo-noise (pn) pattern generator. stimulus from this generator may be used for system testing. the receiver, has a 23rd order signature analyzer that is synchronized to the incoming pn stream and may be used to count character mismatch errors relative to the internal pn reference pattern. this implementation of the 23-bit pn generator and analyzer uses one of the two the polynomials depending on the state of bist_mode_sel: pn equation 1: f = 1 + x 5 + x 23 (bist_mode_sel asserted low) pn equation 2: f = 1 + x 18 + x 23 (bist_mode_sel asserted high) when inter-operating with motorola?s 1.25 gbaud serdes devices (mc92600 or mc92602) use pn equation 1. pn equation 2 is meant for use with external test equipment low high high loop back bist sequence system test mode. high don?t care don?t care reserved. table 5-4. test mode state selection tst_1 tst_0 lbe description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 5. test features 5-5 system accessible test modes that supports this pn equation. either may be used when inter-operating with another mc92610 device as long as both devices use the same pn equation. in addition to using pn equation 2, setting bist_mode_sel high causes the transmitter to insert 2 idle characters for every 2048 pn characters transmit. this makes idles available to be removed to account for frequency offset between devices. the receiver will properly handle the inserted idles when analyzing the pn character stream. note for the two idle characters to be inserted, the adie signal must be asserted. if the adie signal is low, the pn equation 2 is generated with no inserted idles. the total mismatch error count is reset to zero when bist mode is entered. the count is updated continuously while in bist mode. the value of the count is presented on the receiver interface signals: recv_ x _7 through recv_ x _0, making up the eight-bit error count, ordered bits 7 through 0, respectively. the value of the count is sticky in that the count will not wrap to zero upon overflow, but rather, stays at the maximum count value (11111111). the recv_ x _err, recv_ x _k and recv_ x _idle, have special meaning during this test mode. they report the status of the receiver and pn analysis logic. table 5-5 describes the bist error codes and their meaning. the bist sequence makes use of the 8b/10b encoder/decoder. therefore, this test mode overrides the setting on tbie signal and forces byte interface mode. the bist sequence requires that a normal byte alignment mode be used. the setting of bsync is overridden, forcing the device into the byte aligned mode. also, bist exercises all transceivers and their transmission paths, ignoring the setting of lme. finally, the bist logic operates at the reference clock frequency, all received bist data is synchronized to the reference clock frequency, overriding the setting of rcce. bist is run at the speed indicated by the frequency of the reference clock and by the speed range selected by half-speed mode (hse). the settings of wse is not altered and bist will follow its setting order to properly use this test mode, the system must provide the proper stimulus in a special sequence. the sequence is as follows: . table 5-5. bist error codes recv_ x _err recv_ x _k recv_ x _idle description low low low bist running, no pn mismatch this character. high low low bist running, pn mismatch error this character. high low high receiver byte/word synchronized, pn analyzer is not locked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-6 mc92610 serdes user?s manual motorola loop-back bist sequence system test mode step 1: enter test mode by setting the test mode inputs as described in table 5-4. step 2: set reset low and release high; wait pll lock period (~32 s at 3.125 gigabaud). step 3: transmit to the receiver 32 or more idle (k28.5) characters. step 4: transmit to the receiver an 8b/10b encoded pn sequence as described above. the transmitter will automatically go through step 3, transmitting 4,096 idles, and step 4 upon entering this test mode. when testing is complete, the transceiver will need to be resynchronized before normal operation can resume. note the receiver signature analyzers assume all four channels are being exercised. if bist testing is being performed between devices, or by means of external loop back on selected channels, the unused channel receivers must be disabled or the analyzers will not go into the pn sync state. that is, receivers not having an pn stimulus must have xcvr_ x _disable asserted. in link multiplexer mode (lme asserted), the secondary receiver interface (channels b and d), must be disabled. 5.3 loop-back bist sequence system test mode the test mode is the combination of the loop-back and bist sequence system test modes. the device operates as described in section 5.2.1 and section 5.2.2. however, the need to go through the startup sequence is eliminated because the transmitter automatically goes through the proper sequence. high high low not byte sync: the receiver is in start-up or has lost byte alignment and is searching for alignment. high high high not word sync: the receiver is byte synchronized but has not achieved or has lost word alignment and is searching for alignment. table 5-5. bist error codes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 6. electrical specifications and characteristics 6-1 chapter 6 electrical specifications and characteristics this chapter explains the electrical specifications and characteristics for the mc92610 device. this chapter consists of the following sections: section 6.1, ?general characteristics,? section 6.2, ?dc electrical specifications,? and section 6.3, ?ac electrical characteristics.? 6.1 general characteristics this section presents the general technical parameters, the maximum and recommended operating conditions and for the mc92610. 6.1.1 general parameters the following provides a summary of the general parameters of the mc92610: technology?0.25 lithography, hip4 cmos, 5 layer metal package?324 mapbga, 19x19mm body size, 1mm ball pitch core power supply?1.8v + 0.15v dc hstl i/o power supply?1.5v + 0.1 v dc or 1.8v + 0.15v dc link i/o power supply?1.8v + 0.15v dc 6.1.2 absolute maximum ratings the following table 6-1, describes the dc electrical characteristics for the mc92610. table 6-1. absolute maximum ratings characteristics 1 symbol min max unit core supply voltage v dd -0.3 2.2 v pll supply voltage av dd -0.3 2.2 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-2 mc92610 serdes user?s manual motorola general characteristics 6.1.3 recommended operating conditions table 6-2 in this section describes the recommended operating conditions for the mc92610. hstl i/o supply voltage v ddq -0.3 2.2 v link i/o supply voltage xv dd -0.3 2.2 v hstl input voltage v in -0.3 v ddq +0.3 v cmos input voltage v in -0.3 v dd +0.3 v link input voltage v in -0.3 xv dd +0.3 v storage temperature range t stg -55 150 o c esd tolerance hbm 2,000 - v mm 200 - v 1 functional and tested operating conditions are given in table 6-2. absolute maximum ratings are stress ratings only, and functional operation at the maximums are not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. table 6-2. recommended operating conditions characteristic 1, 2 1 these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2 recommended supply power-up order is v dd , av dd , v ddq , xv dd , however, any order is acceptable as long as maximum ratings are not exceeded. symbol min max unit core supply voltage v dd 1.65 1.95 v pll supply voltage av dd 1.65 1.95 v hstl i/o supply voltage (1.5v operation) v ddq 1.40 1.60 v hstl i/o supply voltage (1.8v operation) v ddq 1.65 1.95 v link i/o supply voltage xv dd 1.65 1.95 v hstl input voltage v in 0v ddq v cmos input voltage v in 0v dd v link input voltage v in 0xv dd v junction temperature t j -40 105 o c ambient temperature 3 3 operating ambient temperature is dependent on proper thermal management to meet operating junction temperature t a ?? o c table 6-1. absolute maximum ratings (continued) characteristics 1 symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 6. electrical specifications and characteristics 6-3 dc electrical specifications 6.2 dc electrical specifications table 6-3 in this section describes the mc92610?s electrical characteristics. table 6-3. dc electrical specifications characteristic 1 symbol min max unit core supply current 2 i dd ? 1040 ma pll supply current 2 ai dd ?10ma hstl i/o supply current 2 i ddq ? 240 ma link i/o supply current 2 xi dd ?70ma total power dissipation (typical) 3 p d ??mw hstl reference voltage v ref 0.68 0.9 v hstl input high voltage (dc) v ih dc v ref + 0.1 ?v hstl input low voltage (dc) v il dc - v ref - 0.1 v hstl input high voltage (ac) v ih ac v ref + 0.2 -v hstl input low voltage (ac) v il ac - v ref - 0.2 v hstl input leakage current, v in = v ddq i ih -80 a hstl input leakage current, v in = gnd i il - 275 a hstl output high voltage v oh v ddq -0.4 -v hstl output low voltage v ol -0.4v hstl input capacitance c in -8pf hstl output impedance, vout = v ddq /2 r out 35 55 ? cmos input high voltage v ih 1.0 - v cmos input low voltage v il -0.5v cmos input leakage current, v in = vddq i ih -10 a cmos input leakage current, v in = gnd i il -10 a cmos input capacitance c in -10pf link common mode input impedance r cm 24k ? link differential input impedance (calibration active) r diff 90 115 ? link differential input impedance (calibration disabled) r diff 75 130 ? link common mode input level 4 v cm 0.1 xv dd -0.1 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-4 mc92610 serdes user?s manual motorola ac electrical characteristics 6.3 ac electrical characteristics the figures and tables in this section describe the ac electrical characteristics of mc92610. all specifications stated for t j = -40 c to 105 c, v dd = av dd = xv dd = 1.65v to 1.95v, v ddq = 1.4v to 1.6v. 6.3.1 parallel port interface timing the following figure 6-1 and table 6-4 describe the transmitter ddr interface timing. link differential input amplitude ? v in 0.2 2.2 v p-p link input capacitance c in -3pf link common mode output level v cm 0.725 1.075 v link differential output amplitude, 100 ? diff load (xmit equalization disabled) ? v out 900 1350 mv p-p link differential output impedance r out 80 130 ? 1 v dd = av dd = xv dd = 1.8 + 0.15 v dc, v ddq = 1.5 + 0.1 v dc, gnd = 0 v dc, -40 < t j < 105 c . 2 currents maximums at v dd = av dd = xv dd = v ddq =1.95 v dc, all links terminated, operating at full-speed. 3 p d (typical) mwatts = 208 + 51n + 1.25nf + 3.96f; where n = number of active channels and f = reference frequency in mhz. 4 subject to absolute voltage on link input pin remaining in recommended range per table 6-2. figure 6-1. transmitter ddr interface timing table 6-4. transmitter ddr timing specification symbol characteristic min max unit t 1 1 1 156.25mhz operation setup time to rising/falling edge of xmit_ x _clk 0.480 - ns t 2 1 hold time to rising/falling edge of xmit_ x _clk 0.480 - ns drift phase drift between xmit_ x _clk and ref_clk_p -180 180 degrees table 6-3. dc electrical specifications (continued) characteristic 1 symbol min max unit t 1 t 2 xmit_ x _clk xmit_ x _7?xmit_ x _0 xmit_ x _k xmit _ x _idle t 1 t 2 xmit_a_clk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 6. electrical specifications and characteristics 6-5 ac electrical characteristics the following figure 6-2 and table 6-5 describe the transmitter sdr interface timing. . the following figure 6-3 and table 6-6 describe the receiver ddr interface timing. . figure 6-2. transmitter interface sdr timing diagram (lme = high, ddre = low) table 6-5. transmitter sdr timing specification (lme = high, ddre = low) symbol characteristic min max unit t 1 1 1 156.25mhz operation setup time to rising edge of xmit_ x _clk 0.480 - ns t 2 1 hold time to rising edge of xmit_ x _clk 0.480 - ns figure 6-3. receiver interface ddr timing diagram table 6-6. receiver ddr timing specification symbol characteristic min max unit t 1 output valid time before rising/falling edge of recv_ x _clk 0.96 1 -ns 4.0 2 -ns t 2 output valid time after rising/falling edge of recv_ x _clk 0.96 1 -ns 0.96 2 -ns xmit_ x _clk xmit_ x _7-0 xmit_ x _k xmit _ x _idle t 1 t 2 t 1 t 2 t 1 t 2 t f, t r recv_ x _clk recv_ x _7-0 recv_ x _k recv_ x _idle recv_ x _err recv_ x _9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-6 mc92610 serdes user?s manual motorola ac electrical characteristics the following figure 6-4 and table 6-7 describe the receiver sdr interface timing. . 6.3.2 word synchronization bus timing the following figure 6-5 and table 6-8 describe the word synchronization bus timing. t f 3 output fall time - 1.0 ns t r 3 output rise time - 1.0 ns 1 full speed, 156.25mhz operation (hse = low). 2 half-speed, 78.125mhz operation (hse = high). 3 10pf output load. figure 6-4. receiver interface sdr timing diagram (lme = high, ddre = low) table 6-7. receiver sdr timing specification (lme = high, ddre = low) symbol characteristic min max unit t 1 output valid time before rising edge of recv_ x _clk 4.16 1 1 full speed, 156.25mhz operation (hse = low). -ns 7.36 2 2 half-speed, 78.125mhz operation (hse = high). -ns t 2 output valid time after rising edge of recv_ x _clk 0.96 1 -ns 0.96 2 -ns table 6-6. receiver ddr timing specification (continued) symbol characteristic min max unit recv_ x _clk recv_ x _7-0 recv_ x _k recv_ x _idle recv_ x _err recv_ x _9 t 1 t 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 6. electrical specifications and characteristics 6-7 ac electrical characteristics 6.3.3 reference clock timing the following figure 6-6 and table 6-9 describe the reference clock timing. figure 6-5. word synchronization bus timing diagram table 6-8. word synchronization bus timing specification symbol characteristic min max unit t 1 output valid time before rising edge of ref_clk_p 1.25 1, 2 1 full speed, 156.25mhz operation (hse = low). 2 10 pf output load. -ns 4.45 2, 3 3 half-speed, 78.125mhz operation (hse = high). -ns t 2 output valid time after rising edge of ref_clk_p 1.66 1, 2 -ns 1.66 2, 3 -ns t 3 setup time to rising edge of ref_clk_p -0.25 - ns t 4 hold time to rising edge of ref_clk_p 1.45 - ns figure 6-6. reference clock timing diagram ref_clk_p wso t 3 t 4 wsi t 1 t 2 t f , t r t diff ref_clk_p ref_clk_n 1/f range f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-8 mc92610 serdes user?s manual motorola ac electrical characteristics 6.3.4 receiver recovered clock timing the following figure 6-7 and table 6-10 describe the recovered clock timing. table 6-9. reference clock specification symbol characteristic min max unit t r 1 1 measured between 10-90 percent points. ref_clk_p/n rise time - 2.0 ns t f 1 ref_clk_p/n fall time - 2.0 ns f range ref_clk_p/n frequency range 95 2 2 full speed operation (hse = low). 156.25 mhz 47.5 3 3 half speed operation, not link multiplexer mode (hse = high, lme = low) or half speed operation, link multiplexer mode sdr (lme = high, ddre = low). 78.125 mhz 23.75 4 4 half speed operation (hse = high), link multiplexer mode ddr (lme = high, ddre = high). 39.0625 mhz t d ref_clk_p/n duty cycle 40 60 percent t diff ref_clk_p to ref_clk_n differential skew - 1.0 ns f tol ref_clk_p/n frequency tolerance -100 100 ppm t j 5 5 total peak-to-peak jitter. ref_clk_p/n input jitter - 80 ps t lock 6 6 lock time after compliant ref_clk_p/n signal applied. pll lock time - 20,480 + 25 s bit-times figure 6-7. recovered clock timing diagram table 6-10. recovered clock specification symbol characteristic min max unit t rck recv_ x _clk 6.20 1, 2 -ns 12.44 3 -ns t r 4 recv_ x _rclk rise time - 1.0 ns t f 4 recv_ x _clk fall time - 1.0 ns recv_ x _clk t j t f , t r t rck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 6. electrical specifications and characteristics 6-9 ac electrical characteristics 6.3.5 serial data link timing the following figure 6-8 and table 6-11 describe the link differential output timing. the following figure 6-9 and table 6-12 describe the link differential output timing. t j recv_ x _clk jitter - 400 1, 5 ps -720 3, 5 ps 1 measured between 50-50 percent points, 156.25mhz ref_clk, full speed ddr (hse = low). 2 includes jitter component. 3 measured between 50-50 percent points, 78.125mhz ref_clk, half speed ddr (hse = high). 4 measured between 10-90 percent points. 5 total peak-to-peak jitter. figure 6-8. link differential output timing diagram table 6-11. link differential output specification symbol characteristic min max unit t j 1 1 measured between 50-50 percent points. total jitter - 0.35 ui t dj 1 deterministic jitter - 0.17 ui t ds 1 differential skew - 15 ps x la 2 t 2 rising edge ref_clk_p to bit 0 transmit. transmit latency 150 190 bit-times figure 6-9. link differential input timing diagram table 6-10. recovered clock specification (continued) symbol characteristic min max unit t j t ds xlink0/1_ x _n xlink0/1_ x _p t dstol rlink0/1_ x _n rlink0/1_ x _p t jtol f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-10 mc92610 serdes user?s manual motorola ac electrical characteristics 6.3.6 jtag test port timing the following figure 6-10 and table 6-13 describe the jtag test port timing. table 6-12. link differential input timing specification symbol characteristic min max unit t jtol 1, 2 1 measured between 50-50 percent points . 2 includes 0.1 ui of band-limited sinusoidal noise, 1.875mhz < f noise < 20mhz. total jitter tolerance 0.70 - ui t djtol 1 deterministic jitter tolerance 0.36 - ui t dstol 1 differential skew tolerance 75 - ps r lat receive latency 270 340 3 3 bit 0 at receiver input to parallel data out, no word synchronization. bit-times -400 4 4 bit 0 at receiver input to parallel data out, single-chip word synchronization. bit-times -440 5 5 bit 0 at receiver input to parallel data out, multi-chip word synchronization. bit-times t acq receiver phase acquisition time - 300 6 6 measured with worst-case eye opening, idle pattern, and reference pll locked. bit-times figure 6-10. jtag i/o timing diagram tck tdo tdi tms t 2 t 3 t 1 1/f tck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 6. electrical specifications and characteristics 6-11 ac electrical characteristics table 6-13. jtag i/o timing specification symbol characteristic min max unit note t 1 1 output propagation time after falling edge of tck 1.0 8.0 ns 1 t 2 setup time to rising edge of tck 1.0 - ns t 3 hold time to rising edge of tck 0.5 - ns f tck tck frequency - 20 mhz t d tck duty cycle 35 65 percent 1 10 pf output load f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-12 mc92610 serdes user?s manual motorola ac electrical characteristics f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 7. package description 7-1 chapter 7 package description the following section provides the package parameters and mechanical dimensions of the mc92610 device. the mc92610 is offered in a 324 mapbga package. the 324 mapbga utilizes an aggressive 1 mm ball pitch and 19 mm body size for applications where board space is limited. 7.1 324 mapbga package parameter summary package type?map ball grid array package outline?19 mm x 19 mm package height?1.76 mm (typ.) number of balls?324 ball pitch?1 mm ball diameter?0.63 mm (typ.) 7.2 nomenclature and dimensions of the 324 mapbga package figure 7-1 provides the bottom surface nomenclature and package outline drawing of the 324 mapbga package. figure 7-2 provides the package dimensions. figure 7-3 provides a graphic of the package pin to signal mappings. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-2 mc92610 serdes user?s manual motorola nomenclature and dimensions of the 324 mapbga package figure 7-1. 324 mapbga nomenclature semiconductor products sector copyright motorola, inc. all rights reserved mechanical outlines dictionary do not scale this drawing document no: 98asa99230d page: date: 30 aug 01 rev: a 1344 324 i/o pbga, 19 x 19 pkg, title case number: 1344?02 standard: jedec ms?034 aag?1 package code: 5231 sheet: 1 of 2 x e d y a1 index area top view detail k m m view m?m bottom view s 17x e 0.10 (sheet 2 of 2) 4x 17x e s p n m l k j h g f e d c b a r t u v 12 11 10 6 5 4 3 2 191314 7 8 15 16 17 18 3 0.25 0.10 zxy z 324x b m m a1 index area 1.00 pitch (thick map) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 7. package description 7-3 nomenclature and dimensions of the 324 mapbga package figure 7-2. mapbga dimensions semiconductor products sector 1.86 0.55 0.70 copyright motorola, inc. all rights reserved mechanical outlines dictionary do not scale this drawing document no: 98asa99230d page: date: 30 aug 01 rev: a 1344 title case number: 1344?02 standard: jedec ms?034 aag?1 package code: 5231 sheet: 2 of 2 dim min notes max a a1 a2 b d e e s dimensions are in millimeters. interpret dimensions and tolerances per asme y14.5m?1994. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. datum z (seating plane) is defined by the spherical crowns of the solder balls. parallelism measurement shall exclude any effect of mark on top surface of package. 5 4 3 2 1 1.66 0.45 0.50 1.26 ref 19.00 bsc 19.00 bsc 1.00 bsc 0.50 bsc detail k a a1 z 4 view rotated 90 clockwise a2 324 i/o pbga, 19 x 19 pkg, 1.00 pitch (thick map) 0.20 z 0.25 z 5 324x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-4 mc92610 serdes user?s manual motorola nomenclature and dimensions of the 324 mapbga package . figure 7-3. 324 mapbga package v u t r p n m l k j h g f e d c b a recv_ b_9 tx_ pllv dd recv_ b_idle recv_ b_clk tx_pll_ tpa hstl_ v ref corev dd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ pad gn d coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd xpadgnd recv_ c_err recv_ b_err recv_ c_k tx_ pllgnd corev dd corev dd corev dd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ pad gn d coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd pa dv dd xpadv dd recv_ b_7 recv_ b_k rlink_ b0_p recv_ b_1 rlink_ b1_p corev dd d corev dd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ pad gn d coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd pa dv dd recv_ c_clk recv_ c_9 recv_ c_idle rlink_ c0_p z_calib recv_ c_5 rlink_ c1_p core dd corev dd corev dd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ pad gn d coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd rlink_ b1_n recv_ b_4 recv_ b_5 recv_ b_6 recv_ a_4 rlink_ b0_n corev dd corev dd corev dd corev dd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd recv_ c_6 recv_ c_7 rlink_ c0_ n rlink_ c1_n recv_ c_1 corev dd corev dd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ pad gn d coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd pa dv dd pa dv dd recv_ b_2 recv_ a_5 recv_ b_3 xlink_ b0_p xlink_ b1_p corev dd corev dd corev dd corev dd corev dd corev dd corev dd corev dd corev dd coregnd/ padgnd pa dv dd xpadv dd xpadgnd recv_ c_3 recv_ c_4 recv_ c_2 xlink_ c0_p xlink_ c1_p corev dd corev dd corev dd corev dd corev dd corev dd corev dd corev dd corev dd corev dd coregnd/ padgnd xpadv dd xpadv dd recv_ a_1 recv_ a_0 recv_ b_0 xlink_ b0_n xmit_ a_3 xmit_ a_6 recv_ a_9 recv_ a_clk xcvr_ a_rsel xlink_ b1_n xcvr_ d_rsel corev dd corev dd corev dd corev dd corev dd xpadv dd xpadgnd recv_ d_0 recv_ d_1 xlink_ c0_n xmit_ c_1 recv_ c_0 xlink_ c1_n xmit_ d_5 adie corev dd corev dd corev dd corev dd corev dd corev dd corev dd corev dd xpadgnd xpadgnd bsync tdo recv_ a_2 recv_ a_3 xmit_ b_7 xmit_ b_5 xmit_ a_5 xmit_ a_2 xmit_ b_0 xlink_ a0_p xlink_ a1_p recv_ eq_en bist_ mode_ sel corev dd coregnd/ padgnd pa dv dd xpadv dd xpadgnd recv_ d_2 recv_ d_4 xcvr_a_ disable recv_ d_3 xlink_ d0_p xmit_ c_0 xmit_ c_4 xmit_ c_k xmit_ c_clk recv_ d_clk recv_ d_k xlink_ d1_p lme rcce wse corev dd corev dd xpadgnd trst recv_ ref_a xcvr_ c_rsel recv_ a_6 recv_ a_7 recv_ a_k xmit_ b_6 xmit_ a_7 xmit_ a_4 xmit_ a_0 reset xmit_ b_3 xlink_ a0_n xlink_ a1_n tst_0 coregnd/ padgnd xpadv dd xpadgnd xmit_ d_1 xmit_ c_3 recv_ d_9 recv_ d_5 xmit_ c_7 xmit_ c_idle hse wso repe xmit_ d_idle xcvr_b_ disable xmit_ d_4 xlink_ d0_n xlink_ d1_n xmit_ en_all xpadv dd pa dv dd xpadv dd tdi xmit_ b_idle xmit_ b_4 xmit_ a_clk xmit_ a_1 xmit_ b_2 scan_ en xmit_ a_k recv_ a_idle rlink_ a0_p rlink_ a1_p xcvr_ b_rsel xmit_ ref_a xmit_ eq_en tst_1 coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd xmit_ d_clk xmit_ d_3 xmit_ d_0 pa dv dd wsi xmit_ c_5 ddre lbe lboe xmit_ c_2 xcvr_c_ disable xmit_ d_7 recv_ d_6 rlink_ d0_p rlink_ d1_p corev dd xpadgnd coregnd/ padgnd xmit_ d_6 xmit_ d_2 coregnd/ padgnd recv_ d_err xmit_ c_6 corev dd ref_ clk_n ref_ clk_p xmit_ d_k recv_ d_7 recv_ d_idle xcvr_d_ disable rlink_ d0_n rlink_ d1_n corev dd coregnd/ padgnd coregnd/ padgnd coregnd/ padgnd tms xmit_ b_k xmit_ b_clk xmit_ b_1 tbie drop_ sync xmit_ a_idle recv_ a_err rlink_ a0_n rlink_ a1_n tck corev dd corev dd corev dd corev dd coregnd/ padgnd coregnd/ padgnd pa dv dd 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 18 v u t r p n m l k j h g f e d c b a 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 18 view m?m (bottom view) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 7. package description 7-5 package thermal characteristics 7.3 package thermal characteristics thermal values for the 324 pin mapbga are listed below in table 7-1. the values listed below assume the customer will be mounting these packages on a thermally enhanced mother board. this is defined as a minimum 4-layer board with one ground plane. the values listed below were simulated in accordance with established jedec (joint electron device engineering council) standards. . 7.4 mc92610 chip pinout listing the mc92610 is offered in a 324 mapbga package. table 7-2 lists the mc92610 signal to ball location mappings for the package. also shown are signaling direction (input or output), and the type of logic interfaces. table 7-1. package thermal resistance values symbol description value units ja-0 thermal resistance from junction to ambient, still air 23 ja-2 thermal resistance from junction to ambient, 200 lfm 1 1 linear feet per minute 20 ja-4 thermal resistance from junction to ambient, 400 lfm 1 19 table 7-2. 324 mapbga signal to ball mapping signal name description ball number (324 mapbga) direction i/o type xmit_a_0 transmitter a, data bit 0 t6 input hstl xmit_a_1 transmitter a, data bit 1 u6 input hstl xmit_a_2 transmitter a, data bit 2 r7 input hstl xmit_a_3 transmitter a, data bit 3 p8 input hstl xmit_a_4 transmitter a, data bit 4 t7 input hstl xmit_a_5 transmitter a, data bit 5 r8 input hstl xmit_a_6 transmitter a, data bit 6 p9 input hstl xmit_a_7 transmitter a, data bit 7 t8 input hstl xmit_a_k transmitter a, special character (data bit 8 for tbi mode) u8 input hstl xmit_a_idle transmitter a, idle enable bar, (data bit 9 for tbi mode) v9 input hstl cw ? o cw ? o cw ? o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-6 mc92610 serdes user?s manual motorola mc92610 chip pinout listing xmit_a_clk transmitter a, transmit interface clock u7 input hstl recv_a_0 receiver a, data bit 0 p2 output hstl recv_a_1 receiver a, data bit 1 p3 output hstl recv_a_2 receiver a, data bit 2 r1 output hstl recv_a_3 receiver a, data bit 3 r3 output hstl recv_a_4 receiver a, data bit 4 m4 output hstl recv_a_5 receiver a, data bit 5 n4 output hstl recv_a_6 receiver a, data bit 6 t1 output hstl recv_a_7 receiver a, data bit 7 t2 output hstl recv_a_k receiver a, special character (data bit 8 for tbi mode) t3 output hstl recv_a_9 receiver a, data bit 9 for tbi mode p4 output hstl recv_a_idle receiver a, idle detect u2 output hstl recv_a_err receiver a, error detect v2 output hstl recv_a_clk receiver a, receive data clock p5 output hstl xcvr_a_rsel transceiver a, redundant link select p11 input cmos xcvr_a_disable transceiver a, disable d13 input cmos rlink_a0_p receiver a, primary positive link input u18 input link rlink_a0_n receiver a, primary negative link input v18 input link rlink_a1_p receiver a, redundant positive link input u16 input link rlink_a1_n receiver a, redundant negative link input v16 input link xlink_a0_p transmitter a, primary positive link out r17 output link xlink_a0_n transmitter a, primary negative link out t17 output link xlink_a1_p transmitter a, redundant positive link out r15 output link xlink_a1_n transmitter a, redundant negative link out t15 output link xmit_b_0 transmitter b, data bit 0 r6 input hstl xmit_b_1 transmitter b, data bit 1 v5 input hstl xmit_b_2 transmitter b, data bit 2 u5 input hstl xmit_b_3 transmitter b, data bit 3 t5 input hstl xmit_b_4 transmitter b, data bit 4 u4 input hstl xmit_b_5 transmitter b, data bit 5 r5 input hstl xmit_b_6 transmitter b, data bit 6 t4 input hstl xmit_b_7 transmitter b, data bit 7 r4 input hstl table 7-2. 324 mapbga signal to ball mapping (continued) signal name description ball number (324 mapbga) direction i/o type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 7. package description 7-7 mc92610 chip pinout listing xmit_b_k transmitter b, special character (data bit 8 for tbi mode) v3 input hstl xmit_b_idle transmitter b, idle enable bar, (data bit 9 for tbi mode) u3 input hstl xmit_b_clk transmitter b, transmit interface clock v4 input hstl recv_b_0 receiver b, data bit 0 p1 output hstl recv_b_1 receiver b, data bit 1 l4 output hstl recv_b_2 receiver b, data bit 2 n3 output hstl recv_b_3 receiver b, data bit 3 n1 output hstl recv_b_4 receiver b, data bit 4 m3 output hstl recv_b_5 receiver b, data bit 5 m2 output hstl recv_b_6 receiver b, data bit 6 m1 output hstl recv_b_7 receiver b, data bit 7 l3 output hstl recv_b_k receiver b, special character (data bit 8 for tbi mode) l2 output hstl recv_b_9 receiver b, data bit 9 for tbi mode k2 output hstl recv_b_idle receiver b, idle detect k4 output hstl recv_b_err receiver b, error detect j1 output hstl recv_b_clk receiver b, receive data clock k3 output hstl xcvr_b_rsel transceiver b, redundant link select u13 input cmos xcvr_b_disable transceiver b, disable c14 input cmos rlink_b0_p receiver b, primary positive link input l17 input link rlink_b0_n receiver b, primary negative link input m17 input link rlink_b1_p receiver b, redundant positive link input l15 input link rlink_b1_n receiver b, redundant negative link input m15 input link xlink_b0_p transmitter b, primary positive link out n18 output link xlink_b0_n transmitter b, primary negative link out p18 output link xlink_b1_p transmitter b, redundant positive link out n16 output link xlink_b1_n transmitter b, redundant negative link out p16 output link xmit_c_0 transmitter c, data bit 0 d9 input hstl xmit_c_1 transmitter c, data bit 1 e8 input hstl xmit_c_2 transmitter c, data bit 2 b6 input hstl xmit_c_3 transmitter c, data bit 3 c7 input hstl xmit_c_4 transmitter c, data bit 4 d7 input hstl table 7-2. 324 mapbga signal to ball mapping (continued) signal name description ball number (324 mapbga) direction i/o type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-8 mc92610 serdes user?s manual motorola mc92610 chip pinout listing xmit_c_5 transmitter c, data bit 5 b5 input hstl xmit_c_6 transmitter c, data bit 6 a4 input hstl xmit_c_7 transmitter c, data bit 7 c5 input hstl xmit_c_k transmitter c, special character (data bit 8 for tbi mode) d6 input hstl xmit_c_idle transmitter c, idle enable bar, (data bit 9 for tbi mode) c6 input hstl xmit_c_clk transmitter c, transmit interface clock d8 input hstl recv_c_0 receiver c, data bit 0 e1 output hstl recv_c_1 receiver c, data bit 1 g4 output hstl recv_c_2 receiver c, data bit 2 f3 output hstl recv_c_3 receiver c, data bit 3 f2 output hstl recv_c_4 receiver c, data bit 4 f1 output hstl recv_c_5 receiver c, data bit 5 h4 output hstl recv_c_6 receiver c, data bit 6 g2 output hstl recv_c_7 receiver c, data bit 7 g1 output hstl recv_c_k receiver c, special character (data bit 8 for tbi mode) j4 output hstl recv_c_9 receiver c, data bit 9 for tbi mode h3 output hstl recv_c_idle receiver c, idle detect h1 output hstl recv_c_err receiver c, error detect j2 output hstl recv_c_clk receiver c, receive data clock h2 output hstl xcvr_c_rsel transceiver c, redundant link select t13 input cmos xcvr_c_disable transceiver c, disable b14 input cmos rlink_c0_p receiver c, primary positive link input h17 input link rlink_c0_n receiver c, primary negative link input g17 input link rlink_c1_p receiver c, redundant positive link input h15 input link rlink_c1_n receiver c, redundant negative link input g15 input link xlink_c0_p transmitter c, primary positive link out f18 output link xlink_c0_n transmitter c, primary negative link out e18 output link xlink_c1_p transmitter c, redundant positive link out f16 output link xlink_c1_n transmitter c, redundant negative link out e16 output link xmit_d_0 transmitter d, data bit 0 b7 input hstl xmit_d_1 transmitter d, data bit 1 c8 input hstl table 7-2. 324 mapbga signal to ball mapping (continued) signal name description ball number (324 mapbga) direction i/o type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 7. package description 7-9 mc92610 chip pinout listing xmit_d_2 transmitter d, data bit 2 a7 input hstl xmit_d_3 transmitter d, data bit 3 b8 input hstl xmit_d_4 transmitter d, data bit 4 c9 input hstl xmit_d_5 transmitter d, data bit 5 e9 input hstl xmit_d_6 transmitter d, data bit 6 a8 input hstl xmit_d_7 transmitter d, data bit 7 b9 input hstl xmit_d_k transmitter d, special character (data bit 8 for tbi mode) a9 input hstl xmit_d_idle transmitter d, idle enable bar, (data bit 9 for tbi mode) c10 input hstl xmit_d_clk transmitter d, transmit interface clock b10 input hstl recv_d_0 receiver d, data bit 0 e2 output hstl recv_d_1 receiver d, data bit 1 e3 output hstl recv_d_2 receiver d, data bit 2 d1 output hstl recv_d_3 receiver d, data bit 3 d2 output hstl recv_d_4 receiver d, data bit 4 d3 output hstl recv_d_5 receiver d, data bit 5 c2 output hstl recv_d_6 receiver d, data bit 6 b2 output hstl recv_d_7 receiver d, data bit 7 a1 output hstl recv_d_k receiver d, special character (data bit 8 for tbi mode) d5 output hstl recv_d_9 receiver d, data bit 9 for tbi mode c3 output hstl recv_d_idle receiver d, idle detect a2 output hstl recv_d_err receiver d, error detect a3 output hstl recv_d_clk receiver d, receive data clock d4 output hstl xcvr_d_rsel transceiver d, redundant link select p12 input cmos xcvr_d_disable transceiver d, disable a14 input cmos rlink_d0_p receiver d, primary positive link input b18 input link rlink_d0_n receiver d, primary negative link input a18 input link rlink_d1_p receiver d, redundant positive link input b16 input link rlink_d1_n receiver d, redundant negative link input a16 input link xlink_d0_p transmitter d, primary positive link out d17 output link xlink_d0_n transmitter d, primary negative link out c17 output link xlink_d1_p transmitter d, redundant positive link out d15 output link table 7-2. 324 mapbga signal to ball mapping (continued) signal name description ball number (324 mapbga) direction i/o type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-10 mc92610 serdes user?s manual motorola mc92610 chip pinout listing xlink_d1_n transmitter d, redundant negative link out c15 output link drop_sync drop synchronization v8 input hstl xmit_ref_a transmitter reference clock a select u12 input cmos recv_ref_a receiver reference clock a select t12 input cmos xmit_eq_en transmitter equalization enable u14 input cmos recv_eq_en receiver equalization enable r12 input cmos xmit_en_all transmitter enable, all outputs c12 input cmos tbie ten-bit interface enable v10 input cmos hse half speed enable c13 input cmos ddre double data rate enable b13 input cmos bsync byte synchronization mode r10 input cmos adie add/drop idle enable e10 input cmos repe repeater mode enable c11 input cmos lme link multiplexer mode enable d12 input cmos rcce recovered clock enable d11 input cmos ref_clk_p reference clock positive a13 input hstl ref_clk_n reference clock negative a12 input hstl reset system reset bar t10 input cmos wse word synchronization enable d10 input cmos wso word synchronization bus output c4 output hstl wsi word synchronization bus input b4 input hstl tx_pll_tpa pll analog test point k15 output analog tst_0 test mode select 0 t9 input cmos tst_1 test mode select 1 u9 input cmos scan_en test mode, scan shift enable u10 input cmos lbe loop back enable b12 input cmos lboe loop back output enable b11 input cmos bist_mode_sel bist mode equation select r9 input cmos tdo jtag test data out r11 output hstl tms jtag test mode select v11 input cmos tdi jtag test data in u11 input cmos trst jtag test reset bar t11 input cmos tck jtag test clock v12 input cmos table 7-2. 324 mapbga signal to ball mapping (continued) signal name description ball number (324 mapbga) direction i/o type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola chapter 7. package description 7-11 mc92610 chip pinout listing z_calib impedance calibration reference h18 z ref analog hstl_vref hstl voltage reference k5 v ref analog corev dd core logic supply a5, a10, b15, d14, d18, e4, e5, e6, e7, e11, e12, e13, e14, f4, f5, f6, f7, f8, f9, f10, f11, f12, f14, g14, g18, h5, h14, h16, j5, j14, j17, k14, l5, l14, m5, m14, m16, m18, n5, n6, n7, n8, n9, n10, n11, n12, n14, p6, p7, p10, p13, p14, r14, v6, v13, v15, v17 v dd supply coregnd/padgnd core logic ground / hstl i/o ground a6, a11, a15, a17, b1, f13, g6, g7, g8, g9, g10, g11, g12, g13, g16, h6, h7, h8, h9, h10, h11, h12, h13, j6, j7, j8, j9, j10, j11, j12, j13, j15, k1, k6, k7, k8, k9, k10, k11, k12, k13, k17, l6, l7, l8, l9, l10, l11, l12, l13, l16, l18, m6, m7, m8, m9, m10, m11, m12, m13, n13, r13, t14, u1, u15, u17, v7, v14 gnd ground tx_pllv dd pll analog supply k18 av dd supply tx_pllgnd pll analog ground j18 gnd ground padv dd hstl i/o supply b3, c1, g3, g5, j3, l1, n2, r2, v1 v dd q supply xpadv dd link i/o supply c16, c18, f15, f17, j16, n17, p15, r18, t16 xv dd supply xpadgnd link i/o ground b17, d16, e15, e17, k16, p17, n15, r16, t18 gnd ground table 7-2. 324 mapbga signal to ball mapping (continued) signal name description ball number (324 mapbga) direction i/o type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-12 mc92610 serdes user?s manual motorola mc92610 chip pinout listing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola appendix a. ordering information a-1 appendix a ordering information figure a-1 provides the motorola part numbering nomenclature for the mc92610. for product availability, contact your local motorola semiconductor sales representative. figure a-1. motorola part number key m c 9 2 6 1 0 v f product code: mc = production product part identifier package: vf = 324 pin mapbga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-2 mc92610 serdes user?s manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola appendix b. 8b/10b coding scheme b-1 appendix b 8b/10b coding scheme the mc92610 provides fibre channel-specific 8b/10b encoding and decoding based on the fc-1 fibre channel standard. given 8 bits entering a channel, the 8b/10b encoding converts them to 10 bits thereby increasing the transition density of the serially transmitted signal. b.1 overview the fc-1 standard applies an algorithm that ensures that no more than five 1?s or 0?s are transmitted consecutively, giving a transition density equal to 2.5 for each 10 bit data block. such a density ensures proper dc balance across the link and is sufficient for good clock recovery. in the 8b/10b notation scheme, bytes are referred to as transmission characters, and each bit is represented by letters. unencoded bits, the 8 bits that have not passed through a 8b/10b encoder, are represented by letters ?a? through ?h,? which are bits 0 through7. figure b-1. unencoded transmission character bit ordering encoded bits, those that have passed through an encoder, are represented with the letters ?a? through ?j,? representing bits 0?9 respectively. character (bit) ordering in the fibre channel nomenclature is little-endian, with ?a? being the least significant bit in a byte. one unencoded transmission character (byte) hgfedcba bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
b-2 mc92610 serdes user?s manual motorola overview figure b-2. encoded transmission character bit ordering b.1.1 naming transmission characters transmission characters are given names based on the type of data in the byte and the bit values of the character. two types of transmission characters are specified: data and special. data characters are labeled ?d? characters and special characters are labeled ?k? characters. each transmission character has a bit value and a corresponding decimal value. these elements are combined to provide each character with a name, see table b-1. b.1.2 encoding following is a simplified sequence of steps in 8b/10b coding: 1. an 8-bit block of unencoded data (a transmission character) is picked up by a transmitter. 2. the transmission character is broken into sub-blocks of three bits and five bits. the letters h g and f comprise the 3-bit block, and the letters e d c b and a comprise the 5-bit block. 3. the 3-bit and 5-bit sub-blocks pass through a 3b/4b encoder and a 5b/6b encoder, respectively. a bit is added to each sub-block, such that the transmission character is encoded and expanded to a total of 10-bits. 4. at the time the character is expanded into 10 bits, it is also encoded into the proper running disparity, either positive (rd+) or negative (rd-) depending on certain calculations (see section b.1.3, ?calculating running disparity?). at start-up, the transmitter assumes negative running disparity. one coded transmission character (byte) jhgf iedcba bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb table b-1. components of a character name h g f e d c b a 8b/10b notation 0 0 1 1 1 1 0 0 data bit value 1 28 decimal value of the bit value d or k kind of transmission character k28.1 = data name assigned to this special character f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola appendix b. 8b/10b coding scheme b-3 data tables 5. the positive or negative disparity transmission character (see figure b-3) is passed to the transmit driver, available for differentialization (see section 2.3.1.7, ?transmit driver operation?). figure b-3. character transmission b.1.3 calculating running disparity running disparity improves error detection and recovery. the rules for calculating the running disparity for sub-blocks are as follows (reference fibre channel, gigabit communications and i/o for computer networks ): running disparity at the end of any sub-block is positive if (1) the encoded sub-block contains more 1s than 0s, (2) if the 6-bit sub-block is 6?b00 0111, or (3) if the 4-bit sub-block is 4?b0011. running disparity at the end of any sub-block is negative if (1) the encoded sub-block contains more 0 than 1 bits, (2) if the 6-bit sub-block is 6?b11 1000, or (3) if the 4-bit sub-block is 4?b1100. otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. b.2 data tables table b-2 displays the full valid data character 8b/10b codes. the values in the ?data value hgfedcba? column are the possible bit values of the unencoded transmission characters. the current rd values are the possible positive and negative running disparity values. direction of transmission jhgf i edcba f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
b-4 mc92610 serdes user?s manual motorola data tables table b-2. valid data characters data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj d0.0 000 00000 100111 0100 011000 1011 d0.1 001 00000 100111 1001 011000 1001 d1.0 000 00001 011101 0100 100010 1011 d1.1 001 00001 011101 1001 100010 1001 d2.0 000 00010 101101 0100 010010 1011 d2.1 001 00010 101101 1001 010010 1001 d3.0 000 00011 110001 1011 110001 0100 d3.1 001 00011 110001 1001 110001 1001 d4.0 000 00100 110101 0100 001010 1011 d4.1 001 00100 110101 1001 001010 1001 d5.0 000 00101 101001 1011 101001 0100 d5.1 001 00101 101001 1001 101001 1001 d6.0 000 00110 011001 1011 011001 0100 d6.1 001 00110 011001 1001 011001 1001 d7.0 000 00111 111000 1011 000111 0100 d7.1 001 00111 111000 1001 000111 1001 d8.0 000 01000 111001 0100 000110 1011 d8.1 001 01000 111001 1001 000110 1001 d9.0 000 01001 100101 1011 100101 0100 d9.1 001 01001 100101 1001 100101 1001 d10.0 000 01010 010101 1011 010101 0100 d10.1 001 01010 010101 1001 010101 1001 d11.0 000 01011 110100 1011 110100 0100 d11.1 001 01011 110100 1001 110100 1001 d12.0 000 01100 001101 1011 001101 0100 d12.1 001 01100 001101 1001 001101 1001 d13.0 000 01101 101100 1011 101100 0100 d13.1 001 01101 101100 1001 101100 1001 d14.0 000 01110 011100 1011 011100 0100 d14.1 001 01110 011100 1001 011100 1001 d15.0 000 01111 010111 0100 101000 1011 d15.1 001 01111 010111 1001 101000 1001 d16.0 000 10000 011011 0100 100100 1011 d16.1 001 10000 011011 1001 100100 1001 d17.0 000 10001 100011 1011 100011 0100 d17.1 001 10001 100011 1001 100011 1001 d18.0 000 10010 010011 1011 010011 0100 d18.1 001 10010 010011 1001 010011 1001 d19.0 000 10011 110010 1011 110010 0100 d19.1 001 10011 110010 1001 110010 1001 d20.0 000 10100 001011 1011 001011 0100 d20.1 001 10100 001011 1001 001011 1001 d21.0 000 10101 101010 1011 101010 0100 d21.1 001 10101 101010 1001 101010 1001 d22.0 000 10110 011010 1011 011010 0100 d22.1 001 10110 011010 1001 011010 1001 d23.0 000 10111 111010 0100 000101 1011 d23.1 001 10111 111010 1001 000101 1001 d24.0 000 11000 110011 0100 001100 1011 d24.1 001 11000 110011 1001 001100 1001 d25.0 000 11001 100110 1011 100110 0100 d25.1 001 11001 100110 1001 100110 1001 d26.0 000 11010 010110 1011 010110 0100 d26.1 001 11010 010110 1001 010110 1001 d27.0 000 11011 110110 0100 001001 1011 d27.1 001 11011 110110 1001 001001 1001 d28.0 000 11100 001110 1011 001110 0100 d28.1 001 11100 001110 1001 001110 1001 d29.0 000 11101 101110 0100 010001 1011 d29.1 001 11101 101110 1001 010001 1001 d30.0 000 11110 011110 0100 100001 1011 d30.1 001 11110 011110 1001 100001 1001 d31.0 000 11111 101011 0100 010100 1011 d31.1 001 11111 101011 1001 010100 1001 d0.2 010 00000 100111 0101 011000 0101 d0.3 011 00000 100111 0011 011000 1100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola appendix b. 8b/10b coding scheme b-5 data tables d1.2 010 00001 011101 0101 100010 0101 d1.3 011 00001 011101 0011 100010 1100 d2.2 010 00010 101101 0101 010010 0101 d2.3 011 00010 101101 0011 010010 1100 d3.2 010 00011 110001 0101 110001 0101 d3.3 011 00011 110001 1100 110001 0011 d4.2 010 00100 110101 0101 001010 0101 d4.3 011 00100 110101 0011 001010 1100 d5.2 010 00101 101001 0101 101001 0101 d5.3 011 00101 101001 1100 101001 0011 d6.2 010 00110 011001 0101 011001 0101 d6.3 011 00110 011001 1100 011001 0011 d7.2 010 00111 111000 0101 000111 0101 d7.3 011 00111 111000 1100 000111 0011 d8.2 010 01000 111001 0101 000110 0101 d8.3 011 01000 111001 0011 000110 1100 d9.2 010 01001 100101 0101 100101 0101 d9.3 011 01001 100101 1100 100101 0011 d10.2 010 01010 010101 0101 010101 0101 d10.3 011 01010 010101 1100 010101 0011 d11.2 010 01011 110100 0101 110100 0101 d11.3 011 01011 110100 1100 110100 0011 d12.2 010 01100 001101 0101 001101 0101 d12.3 011 01100 001101 1100 001101 0011 d13.2 010 01101 101100 0101 101100 0101 d13.3 011 01101 101100 1100 101100 0011 d14.2 010 01110 011100 0101 011100 0101 d14.3 011 01110 011100 1100 011100 0011 d15.2 010 01111 010111 0101 101000 0101 d15.3 011 01111 010111 0011 101000 1100 d16.2 010 10000 011011 0101 100100 0101 d16.3 011 10000 011011 0011 100100 1100 d17.2 010 10001 100011 0101 100011 0101 d17.3 011 10001 100011 1100 100011 0011 d18.2 010 10010 010011 0101 010011 0101 d18.3 011 10010 010011 1100 010011 0011 d19.2 010 10011 110010 0101 110010 0101 d19.3 011 10011 110010 1100 110010 0011 d20.2 010 10100 001011 0101 001011 0101 d20.3 011 10100 001011 1100 001011 0011 d21.2 010 10101 101010 0101 101010 0101 d21.3 011 10101 101010 1100 101010 0011 d22.2 010 10110 011010 0101 011010 0101 d22.3 011 10110 011010 1100 011010 0011 d23.2 010 10111 111010 0101 000101 0101 d23.3 011 10111 111010 0011 000101 1100 d24.2 010 11000 110011 0101 001100 0101 d24.3 011 11000 110011 0011 001100 1100 d25.2 010 11001 100110 0101 100110 0101 d25.3 011 11001 100110 1100 100110 0011 d26.2 010 11010 010110 0101 010110 0101 d26.3 011 11010 010110 1100 010110 0011 d27.2 010 11011 110110 0101 001001 0101 d27.3 011 11011 110110 0011 001001 1100 d28.2 010 11100 001110 0101 001110 0101 d28.3 011 11100 001110 1100 001110 0011 d29.2 010 11101 101110 0101 010001 0101 d29.3 011 11101 101110 0011 010001 1100 d30.2 010 11110 011110 0101 100001 0101 d30.3 011 11110 011110 0011 100001 1100 d31.2 010 11111 101011 0101 010100 0101 d31.3 011 11111 101011 0011 010100 1100 d0.4 100 00000 100111 0010 011000 1101 d0.5 101 00000 100111 1010 011000 1010 d1.4 100 00001 011101 0010 100010 1101 d1.5 101 00001 011101 1010 100010 1010 table b-2. valid data characters (continued) data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
b-6 mc92610 serdes user?s manual motorola data tables d2.4 100 00010 101101 0010 010010 1101 d2.5 101 00010 101101 1010 010010 1010 d3.4 100 00011 110001 1101 110001 0010 d3.5 101 00011 110001 1010 110001 1010 d4.4 100 00100 110101 0010 001010 1101 d4.5 101 00100 110101 1010 001010 1010 d5.4 100 00101 101001 1101 101001 0010 d5.5 101 00101 101001 1010 101001 1010 d6.4 100 00110 011001 1101 011001 0010 d6.5 101 00110 011001 1010 011001 1010 d7.4 100 00111 111000 1101 000111 0010 d7.5 101 00111 111000 1010 000111 1010 d8.4 100 01000 111001 0010 000110 1101 d8.5 101 01000 111001 1010 000110 1010 d9.4 100 01001 100101 1101 100101 0010 d9.5 101 01001 100101 1010 100101 1010 d10.4 100 01010 010101 1101 010101 0010 d10.5 101 01010 010101 1010 010101 1010 d11.4 100 01011 110100 1101 110100 0010 d11.5 101 01011 110100 1010 110100 1010 d12.4 100 01100 001101 1101 001101 0010 d12.5 101 01100 001101 1010 001101 1010 d13.4 100 01101 101100 1101 101100 0010 d13.5 101 01101 101100 1010 101100 1010 d14.4 100 01110 011100 1101 011100 0010 d14.5 101 01110 011100 1010 011100 1010 d15.4 100 01111 010111 0010 101000 1101 d15.5 101 01111 010111 1010 101000 1010 d16.4 100 10000 011011 0010 100100 1101 d16.5 101 10000 011011 1010 100100 1010 d17.4 100 10001 100011 1101 100011 0010 d17.5 101 10001 100011 1010 100011 1010 d18.4 100 10010 010011 1101 010011 0010 d18.5 101 10010 010011 1010 010011 1010 d19.4 100 10011 110010 1101 110010 0010 d19.5 101 10011 110010 1010 110010 1010 d20.4 100 10100 001011 1101 001011 0010 d20.5 101 10100 001011 1010 001011 1010 d21.4 100 10101 101010 1101 101010 0010 d21.5 101 10101 101010 1010 101010 1010 d22.4 100 10110 011010 1101 011010 0010 d22.5 101 10110 010101 1010 011010 1010 d23.4 100 10111 111010 0010 000101 1101 d23.5 101 10111 111010 1010 000101 1010 d24.4 100 11000 110011 0010 001100 1101 d24.5 101 11000 110011 1010 001100 1010 d25.4 100 11001 100110 1101 100110 0010 d25.5 101 11001 100110 1010 100110 1010 d26.4 100 11010 010110 1101 010110 0010 d26.5 101 11010 010110 1010 010110 1010 d27.4 100 11011 110110 0010 001001 1101 d27.5 101 11011 110110 1010 001001 1010 d28.4 100 11100 001110 1101 001110 0010 d28.5 101 11100 001110 1010 001110 1010 d29.4 100 11101 101110 0010 010001 1101 d29.5 101 11101 101110 1010 010001 1010 d30.4 100 11110 011110 0010 100001 1101 d30.5 101 11110 011110 1010 100001 1010 d31.4 100 11111 101011 0010 010100 1101 d31.5 101 11111 101011 1010 010100 1010 d0.6 110 00000 100111 0110 011000 0110 d0.7 111 00000 100111 0001 011000 1110 d1.6 110 00001 011101 0110 100010 0110 d1.7 111 00001 011101 0001 100010 1110 d2.6 110 00010 101101 0110 010010 0110 d2.7 111 00010 101101 0001 010010 1110 table b-2. valid data characters (continued) data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola appendix b. 8b/10b coding scheme b-7 data tables d3.6 110 00011 110001 0110 110001 0110 d3.7 111 00011 110001 1110 110001 0001 d4.6 110 00100 110101 0110 001010 0110 d4.7 111 00100 110101 0001 001010 1110 d5.6 110 00101 101001 0110 101001 0110 d5.7 111 00101 101001 1110 101001 0001 d6.6 110 00110 011001 0110 011001 0110 d6.7 111 00110 011001 1110 011001 0001 d7.6 110 00111 111000 0110 000111 0110 d7.7 111 00111 111000 1110 000111 0001 d8.6 110 01000 111001 0110 000110 0110 d8.7 111 01000 111001 0001 000110 1110 d9.6 110 01001 100101 0110 100101 0110 d9.7 111 01001 100101 1110 100101 0001 d10.6 110 01010 010101 0110 010101 0110 d10.7 111 01010 010101 1110 010101 0001 d11.6 110 01011 110100 0110 110100 0110 d11.7 111 01011 110100 1110 110100 1000 d12.6 110 01100 001101 0110 001101 0110 d12.7 111 01100 001101 1110 001101 0001 d13.6 110 01101 101100 0110 101100 0110 d13.7 111 01101 101100 1110 101100 1000 d14.6 110 01110 011100 0110 011100 0110 d14.7 111 01110 011100 1110 011100 1000 d15.6 110 01111 010111 0110 101000 0110 d15.7 111 01111 010111 0001 101000 1110 d16.6 110 10000 011011 0110 100100 0110 d16.7 111 10000 011011 0001 100100 1110 d17.6 110 10001 100011 0110 100011 0110 d17.7 111 10001 100011 0111 100011 0001 d18.6 110 10010 010011 0110 010011 0110 d18.7 111 10010 010011 0111 010011 0001 d19.6 110 10011 110010 0110 110010 0110 d19.7 111 10011 110010 1110 110010 0001 d20.6 110 10100 001011 0110 001011 0110 d20.7 111 10100 001011 0111 001011 0001 d21.6 110 10101 101010 0110 101010 0110 d21.7 111 10101 101010 1110 101010 0001 d22.6 110 10110 011010 0110 011010 0110 d22.7 111 10110 011010 1110 011010 0001 d23.6 110 10111 111010 0110 000101 0110 d23.7 111 10111 111010 0001 000101 1110 d24.6 110 11000 110011 0110 001100 0110 d24.7 111 11000 110011 0001 001100 1110 d25.6 110 11001 100110 0110 100110 0110 d25.7 111 11001 100110 1110 100110 0001 d26.6 110 11010 010110 0110 010110 0110 d26.7 111 11010 010110 1110 010110 0001 d27.6 110 11011 110110 0110 001001 0110 d27.7 111 11011 110110 0001 001001 1110 d28.6 110 11100 001110 0110 001110 0110 d28.7 111 11100 001110 1110 001110 0001 d29.6 110 11101 101110 0110 010001 0110 d29.7 111 11101 101110 0001 010001 1110 d30.6 110 11110 011110 0110 100001 0110 d30.7 111 11110 011110 0001 100001 1110 d31.6 110 11111 101011 0110 010100 0110 d31.7 111 11111 101011 0001 010100 1110 table b-2. valid data characters (continued) data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj data name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
b-8 mc92610 serdes user?s manual motorola data tables table b-3 displays the full valid special character 8b/10b codes. table b-3. valid special characters name data value hgf edcba current rd- abcdei fghj current rd+ abcdei fghj name data value hgf edcba current rd- abcdei fghj current rd+ abcdie fghj k28.0 000 11100 001111 0100 110000 1011 k28.6 110 11100 001111 0110 110000 1001 k28.1 001 11100 001111 1001 110000 0110 k28.7 111 11100 001111 1000 110000 0111 k28.2 010 11100 001111 0101 110000 1010 k23.7 111 10111 111010 1000 000101 0111 k28.3 011 11100 001111 0011 110000 1100 k27.7 111 11011 110110 1000 001001 0111 k28.4 100 11100 001111 0010 110000 1101 k29.7 111 11101 101110 1000 010001 0111 k28.5 101 11100 001111 1010 110000 0101 k30.7 111 11110 011110 1000 100001 0111 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola glossary glossary-1 glossary of terms and abbreviations the glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. some of the terms and definitions included in the glossary are reprinted from ieee std 754-1985, ieee standard for binary floating-point arithmetic , copyright ?1985 by the institute of electrical and electronics engineers, inc., with the permission of the ieee. a asserted . indicates active state of signal has been set. refers to either inputs or outputs. b berc . bit error rate checking. bert . bit error rate testing. bist . built-in self-test. bit alignment . refers to the transition tracking loop recovering data bits from the serial input stream. byte . eight bits of uncoded data. byte alignment . receiver identification of character boundaries through use of idle character recognition. c character . an 8b/10b encoded byte of data. g gigabit . a unit of speed of data transfer. one gigabit indicates a data throughput of 1 billion bits per second requiring a transfer rate of 1.25 billion symbols per second of 8b/10b encoded data. gigabaud . a unit of speed of symbol transfer. one gigabaud indicates a data throughput of 800 million bits per second requiring a transfer rate of 1.0 billion symbols per second of 8b/10b encoded data. i isi . inter symbol interference, a distortion caused by the high-frequency loss characteristics of the transmission media. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
glossary-2 mc92610 serdes user?s manual motorola n negated . indicates inactive state of signal has been set. refers to either inputs or outputs. p pll . phase locked loop. ppm . parts per million. r running disparity . the amount of dc imbalance over a history of symbols transmitted over a link. equal to the difference between the number of one and zero symbols transmitted. s symbol . one piece of information sent across the link; different from a bit in that bit implies data where symbol is encoded data. w word synchronization . alignment of four or more receivers? data by adjusting for differences in media and systemic delay between them such that data is presented by the receivers in the same grouping as they were transmit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index motorola index index-1 numerics 8b/10b coding scheme, b-1 decoder, 3-13 encoder operation, 2-7 encoder/decoder, 5-5 encoding sequence of, b-2 notation, b-1 a absolute maximum ratings, 6-1 ac electrical characteristics, 6-4 add/drop idle mode, 4-4 alignment loss, 3-9 b bist error codes, 5-5 boundary-scan register, 5-3 byte alignment, 3-8 interface, 3-14, 3-15 byte interface mode, 3-14 c configuration and control signals, 4-4 conventions, xv d data recovery, 3-8 dc electrical specifications, 6-3 device identification register, 5-3 disparity calculating, b-3 double data rate mode, 4-4 e electrical characteristics, 6-1 specifications, 6-1 f features, 1-1 frequency offset, 3-8, 3-12, 3-16 functional description, 2-5 g general parameters, 6-1 h half-speed mode, 3-17, 4-4 hstl reference voltage recommendation, 4-6 i ieee std. 1149.1 implementation, 5-1 impedance control reference recommendation, 4-7 input amplifier, 3-6 instruction register, 5-2 instructions, 5-2 j jtag i/o timing diagram, 6-10 i/o timing specification, 6-10 l link differential input timing diagram, 6-9 input timing specification, 6-10 output specification, 6-9 output timing diagram, 6-9 link multiplexer mode, 2-6, 3-17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index-2 mc92610 serdes user?s manual motorola loop, 5-6 loop-back bist sequence system test mode, 5-6 loop-back test mode, 2-8 m mc92610 block diagram, 1-2 overview, 1-1 modes half-speed mode, 3-17 link multiplexer mode, 3-17 recovered clock timing mode, 3-16 reference clock timing mode, 3-16 repeater mode, 3-17 o operating conditions, 6-2 p package description, 7-1 nomenclature and dimensions, 7-1 parameter summary, 7-1 pinout listing, 7-5 thermal characteristics, 7-5 performance, 5-3 phase locked loop (pll) power supply filtering, 4-5 pinout listing, 7-5 power supply, 6-1 power supply decoupling recommendations, 4-6 requirements, 4-5 production testing, 5-1 proper running disparity, b-2 r realignment method, 3-8 receiver, 3-1 block diagram, 3-2 ddr timing specification, 6-5 equalization, 3-7 functional description, 3-5 interface, 3-13 interface ddr timing diagram, 6-5 interface error codes, 3-14, 3-15 interface sdr timing diagram, 6-6 interface signals, 3-2, 3-3 sdr timing specification, 6-6 recovered clock mode, 4-3 specification, 6-8 timing diagram, 6-8 timing mode, 3-16 reference clock specification, 6-8 timing diagram, 6-7 timing mode, 3-16 references, 1-4 repeater mode, 2-7, 3-17 revision history, 1-4 s startup, 4-2 t tap interface signals, 5-1 ten-bit interface, 3-14, 3-15 ten-bit interface mode, 4-2 test access port interface signals, 5-1 test modes loop-back bist sequence system test mode, 5-6 transition density, b-1 transition tracking loop, 3-8 transition tracking loop and data recovery, 3-8 transmission characters naming, types, b-2 overview, b-1 transmit data input register operation, 2-5 transmit driver operation, 2-8 transmit equalization, 2-8 transmit interface clock configuration, 2-7 transmitter, 2-1 block diagram, 2-2 ddr interface timing, 6-4 ddr timing specification, 6-4 interface sdr timing diagram, 6-5 interface signals, 2-2 sdr timing specification, 6-5 transmitter control states, 2-5 transmitter interface signals, 2-2 transmitting, 2-5 transmitting pre-coded data, 2-6 transmitting uncoded data, 2-5 u uncoded data in 8b/10b coding scheme, b-1 v voltage reference for single-ended reference clock use, 4-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola index index-3 w word synchronization bus, 3-11 bus timing diagram, 6-7 bus timing specification, 6-7 mode, 4-3 states, 3-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index-4 mc92610 serdes user?s manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview transmitter receiver system design considerations package description index test features electrical specifications and characteristics 1 2 3 4 5 6 7 ind glossary of terms and abbreviations glo 8b/10b coding scheme ordering information a b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview transmitter receiver system design considerations package description glossary of terms and abbreviations index 1 2 3 4 5 6 7 glo ind test features electrical specifications and characteristics 8b/10b coding scheme a b ordering information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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